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Re: [PATCH v3 4/5] [RISCV_PM] Support pointer masking for RISC-V for i/c
From: |
Richard Henderson |
Subject: |
Re: [PATCH v3 4/5] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions |
Date: |
Fri, 16 Oct 2020 16:49:06 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 10/16/20 3:11 PM, Alexey Baturo wrote:
> Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
> ---
> target/riscv/insn_trans/trans_rva.c.inc | 3 +++
> target/riscv/insn_trans/trans_rvd.c.inc | 2 ++
> target/riscv/insn_trans/trans_rvf.c.inc | 2 ++
> target/riscv/insn_trans/trans_rvi.c.inc | 2 ++
> target/riscv/translate.c | 14 ++++++++++++++
> 5 files changed, 23 insertions(+)
This will need changes for RVV, but let's omit that for now, so as not to race
with the in-flight update to rvv-1.0.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
- [PATCH v3 0/5] RISC-V Pointer Masking implementation, Alexey Baturo, 2020/10/16
- [PATCH v3 1/5] [RISCV_PM] Add J-extension into RISC-V, Alexey Baturo, 2020/10/16
- [PATCH v3 5/5] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension, Alexey Baturo, 2020/10/16
- [PATCH v3 4/5] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions, Alexey Baturo, 2020/10/16
- Re: [PATCH v3 4/5] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions,
Richard Henderson <=
- [PATCH v3 3/5] [RISCV_PM] Print new PM CSRs in QEMU logs, Alexey Baturo, 2020/10/16
- [PATCH v3 2/5] [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode, Alexey Baturo, 2020/10/16
- Re: [PATCH v3 0/5] RISC-V Pointer Masking implementation, no-reply, 2020/10/16