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[PATCH v2 3/5] [RISCV_PM] Print new PM CSRs in QEMU logs
From: |
Alexey Baturo |
Subject: |
[PATCH v2 3/5] [RISCV_PM] Print new PM CSRs in QEMU logs |
Date: |
Thu, 15 Oct 2020 18:21:37 +0300 |
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
---
target/riscv/cpu.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d63031eb08..6ba3e98508 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -255,6 +255,25 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,
int flags)
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
}
+ if (riscv_has_ext(env, RVJ)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mmte ", env->mmte);
+ switch (env->priv) {
+ case PRV_U:
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmbase ",
env->upmbase);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmmask ",
env->upmmask);
+ break;
+ case PRV_S:
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmbase ",
env->spmbase);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmmask ",
env->spmmask);
+ break;
+ case PRV_M:
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmbase ",
env->mpmbase);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmmask ",
env->mpmmask);
+ break;
+ default:
+ assert(0 && "Unreachable");
+ }
+ }
#endif
for (i = 0; i < 32; i++) {
--
2.20.1
[PATCH v2 3/5] [RISCV_PM] Print new PM CSRs in QEMU logs,
Alexey Baturo <=
[PATCH v2 4/5] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions, Alexey Baturo, 2020/10/15
[PATCH v2 5/5] [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension, Alexey Baturo, 2020/10/15