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[PATCH v2] target/arm: Allow user-mode code to write CPSR.E via MSR
From: |
Peter Maydell |
Subject: |
[PATCH v2] target/arm: Allow user-mode code to write CPSR.E via MSR |
Date: |
Mon, 12 Oct 2020 16:33:51 +0100 |
Using the MSR instruction to write to CPSR.E is deprecated, but it is
required to work from any mode including unprivileged code. We were
incorrectly forbidding usermode code from writing it because
CPSR_USER did not include the CPSR_E bit.
We use CPSR_USER in only three places:
* as the mask of what to allow userspace MSR to write to CPSR
* when deciding what bits a linux-user signal-return should be
able to write from the sigcontext structure
* in target_user_copy_regs() when we set up the initial
registers for the linux-user process
In the first two cases not being able to update CPSR.E is a bug, and
in the third case it doesn't matter because CPSR.E is always 0 there.
So we can fix both bugs by adding CPSR_E to CPSR_USER.
Because the cpsr_write() in restore_sigcontext() is now changing
a CPSR bit which is cached in hflags, we need to add an
arm_rebuild_hflags() call there; the callsite in
target_user_copy_regs() was already rebuilding hflags for other
reasons.
(The recommended way to change CPSR.E is to use the 'SETEND'
instruction, which we do correctly allow from usermode code.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
v2 changes:
* fixed wrong variable name in commit message
* added arm_rebuild_hflags() call in restore_sigcontext()
---
target/arm/cpu.h | 2 +-
linux-user/arm/signal.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 5d995368d4f..677584e5da0 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1230,7 +1230,7 @@ void pmu_init(ARMCPU *cpu);
#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
| CPSR_NZCV)
/* Bits writable in user mode. */
-#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
+#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
/* Execution state bits. MRS read as zero, MSR writes ignored. */
#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c
index a475a103e97..698985a647e 100644
--- a/linux-user/arm/signal.c
+++ b/linux-user/arm/signal.c
@@ -552,6 +552,7 @@ restore_sigcontext(CPUARMState *env, struct
target_sigcontext *sc)
#ifdef TARGET_CONFIG_CPU_32
__get_user(cpsr, &sc->arm_cpsr);
cpsr_write(env, cpsr, CPSR_USER | CPSR_EXEC, CPSRWriteByInstr);
+ arm_rebuild_hflags(env);
#endif
err |= !valid_user_regs(env);
--
2.20.1
- [PATCH for-5.1] hw/timer/imx_epit: Avoid assertion when CR.SWR is written, (continued)
- [PATCH for-5.1] hw/timer/imx_epit: Avoid assertion when CR.SWR is written, Peter Maydell, 2020/10/12
- [PATCH] hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work, Peter Maydell, 2020/10/12
- [RFC PATCH v2] linux-user: Use FD_32BIT_MODE fd flag for 32-bit guests, Peter Maydell, 2020/10/12
- [PATCH] linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32, Peter Maydell, 2020/10/12
- [PATCH] msf2-soc, stellaris: Don't wire up SYSRESETREQ, Peter Maydell, 2020/10/12
- [PATCH] meson.build: Don't look for libudev for static builds, Peter Maydell, 2020/10/12
- [PATCH] target/arm: Delete unused ARM_FEATURE_CRC, Peter Maydell, 2020/10/12
- [PATCH] net/tap-solaris.c: Include qemu-common.h for TFR macro, Peter Maydell, 2020/10/12
- [PATCH] target/arm: Delete unused VFP_DREG macros, Peter Maydell, 2020/10/12
- [PATCH] osdep.h: Add doc comment for qemu_get_thread_id(), Peter Maydell, 2020/10/12
- [PATCH v2] target/arm: Allow user-mode code to write CPSR.E via MSR,
Peter Maydell <=
- [PATCH for-5.1] qapi/machine.json: Fix missing newline in doc comment, Peter Maydell, 2020/10/12
- [PATCH 00/10] target/arm: Various v8.1M minor features, Peter Maydell, 2020/10/12
- [PATCH 01/10] decodetree: Fix codegen for non-overlapping group inside overlapping group, Peter Maydell, 2020/10/12
- [PATCH 02/10] target/arm: Implement v8.1M NOCP handling, Peter Maydell, 2020/10/12
- [PATCH 03/10] target/arm: Implement v8.1M conditional-select insns, Peter Maydell, 2020/10/12
- [PATCH 04/10] target/arm: Make the t32 insn[25:23]=111 group non-overlapping, Peter Maydell, 2020/10/12
- [PATCH 09/10] target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension, Peter Maydell, 2020/10/12