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[PATCH V2 0/5] Support RISC-V migration
From: |
Yifei Jiang |
Subject: |
[PATCH V2 0/5] Support RISC-V migration |
Date: |
Sat, 10 Oct 2020 16:06:18 +0800 |
This patches supported RISC-V migration based on tcg accel. And we have
verified related migration features such as snapshot and live migration.
A few weeks ago, we submitted RFC patches about supporting RISC-V migration
based on kvm accel: https://www.spinics.net/lists/kvm/msg223605.html.
And we found that tcg accelerated migration can be supported with a few
changes. Most of the devices have already implemented the migration
interface, so, to achieve the tcg accelerated migration, we just need to
add vmstate of both cpu and sifive_plic.
Changes since v1:
1. Add license head to target/riscv/machine.c.
2. Regenerate some state of PMP at post_load hook.
Yifei Jiang (5):
target/riscv: Add basic vmstate description of CPU
target/riscv: Add PMP state description
target/riscv: Add H extension state description
target/riscv: Add V extension state description
target/riscv: Add sifive_plic vmstate
hw/intc/sifive_plic.c | 26 ++++-
hw/intc/sifive_plic.h | 1 +
target/riscv/cpu.c | 7 --
target/riscv/cpu.h | 4 +
target/riscv/machine.c | 203 +++++++++++++++++++++++++++++++++++++++
target/riscv/meson.build | 3 +-
target/riscv/pmp.c | 29 +++---
target/riscv/pmp.h | 2 +
8 files changed, 255 insertions(+), 20 deletions(-)
create mode 100644 target/riscv/machine.c
--
2.19.1
- [PATCH V2 0/5] Support RISC-V migration,
Yifei Jiang <=
[PATCH V2 4/5] target/riscv: Add V extension state description, Yifei Jiang, 2020/10/10
[PATCH V2 3/5] target/riscv: Add H extension state description, Yifei Jiang, 2020/10/10
[PATCH V2 5/5] target/riscv: Add sifive_plic vmstate, Yifei Jiang, 2020/10/10
[PATCH V2 2/5] target/riscv: Add PMP state description, Yifei Jiang, 2020/10/10