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[RFC v5 58/68] target/riscv: rvv-1.0: floating-point min/max instruction
From: |
frank . chang |
Subject: |
[RFC v5 58/68] target/riscv: rvv-1.0: floating-point min/max instructions |
Date: |
Wed, 30 Sep 2020 03:04:33 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/vector_helper.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index c5e6572012..e3056a06fe 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3596,28 +3596,28 @@ GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4)
GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8)
/* Vector Floating-Point MIN/MAX Instructions */
-RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum)
-RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum)
-RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minnum)
+RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum_noprop)
+RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum_noprop)
+RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minnum_noprop)
GEN_VEXT_VV_ENV(vfmin_vv_h, 2, 2)
GEN_VEXT_VV_ENV(vfmin_vv_w, 4, 4)
GEN_VEXT_VV_ENV(vfmin_vv_d, 8, 8)
-RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minnum)
-RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minnum)
-RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minnum)
+RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minnum_noprop)
+RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minnum_noprop)
+RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minnum_noprop)
GEN_VEXT_VF(vfmin_vf_h, 2, 2)
GEN_VEXT_VF(vfmin_vf_w, 4, 4)
GEN_VEXT_VF(vfmin_vf_d, 8, 8)
-RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maxnum)
-RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maxnum)
-RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maxnum)
+RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maxnum_noprop)
+RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maxnum_noprop)
+RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maxnum_noprop)
GEN_VEXT_VV_ENV(vfmax_vv_h, 2, 2)
GEN_VEXT_VV_ENV(vfmax_vv_w, 4, 4)
GEN_VEXT_VV_ENV(vfmax_vv_d, 8, 8)
-RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maxnum)
-RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maxnum)
-RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum)
+RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maxnum_noprop)
+RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maxnum_noprop)
+RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum_noprop)
GEN_VEXT_VF(vfmax_vf_h, 2, 2)
GEN_VEXT_VF(vfmax_vf_w, 4, 4)
GEN_VEXT_VF(vfmax_vf_d, 8, 8)
--
2.17.1
- [RFC v5 48/68] target/riscv: rvv-1.0: mask-register logical instructions, (continued)
- [RFC v5 48/68] target/riscv: rvv-1.0: mask-register logical instructions, frank . chang, 2020/09/29
- [RFC v5 49/68] target/riscv: rvv-1.0: slide instructions, frank . chang, 2020/09/29
- [RFC v5 51/68] target/riscv: rvv-1.0: narrowing fixed-point clip instructions, frank . chang, 2020/09/29
- [RFC v5 50/68] target/riscv: rvv-1.0: floating-point slide instructions, frank . chang, 2020/09/29
- [RFC v5 52/68] target/riscv: rvv-1.0: single-width floating-point reduction, frank . chang, 2020/09/29
- [RFC v5 53/68] target/riscv: rvv-1.0: widening floating-point reduction instructions, frank . chang, 2020/09/29
- [RFC v5 54/68] target/riscv: rvv-1.0: single-width scaling shift instructions, frank . chang, 2020/09/29
- [RFC v5 55/68] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add, frank . chang, 2020/09/29
- [RFC v5 56/68] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf, frank . chang, 2020/09/29
- [RFC v5 57/68] target/riscv: rvv-1.0: remove integer extract instruction, frank . chang, 2020/09/29
- [RFC v5 58/68] target/riscv: rvv-1.0: floating-point min/max instructions,
frank . chang <=
- [RFC v5 59/68] target/riscv: introduce floating-point rounding mode enum, frank . chang, 2020/09/29
- [RFC v5 60/68] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, frank . chang, 2020/09/29
- [RFC v5 61/68] target/riscv: rvv-1.0: widening floating-point/integer type-convert, frank . chang, 2020/09/29
- [RFC v5 62/68] target/riscv: add "set round to odd" rounding mode helper function, frank . chang, 2020/09/29
- [RFC v5 63/68] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 2020/09/29
- [RFC v5 64/68] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits, frank . chang, 2020/09/29
- [RFC v5 65/68] target/riscv: gdb: modify gdb csr xml file to align with csr register map, frank . chang, 2020/09/29
- [RFC v5 66/68] target/riscv: gdb: support vector registers for rv64 & rv32, frank . chang, 2020/09/29
- [RFC v5 68/68] target/riscv: trigger illegal instruction exception if frm is not valid, frank . chang, 2020/09/29
- [RFC v5 67/68] target/riscv: implement vstart CSR, frank . chang, 2020/09/29