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[PATCH v3 23/81] target/arm: Implement SVE2 integer add/subtract long wi
From: |
Richard Henderson |
Subject: |
[PATCH v3 23/81] target/arm: Implement SVE2 integer add/subtract long with carry |
Date: |
Fri, 18 Sep 2020 11:36:53 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Fix sel indexing and argument order (laurent desnogues).
---
target/arm/helper-sve.h | 3 +++
target/arm/sve.decode | 6 ++++++
target/arm/sve_helper.c | 34 ++++++++++++++++++++++++++++++++++
target/arm/translate-sve.c | 23 +++++++++++++++++++++++
4 files changed, 66 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index d5dfd4edea..a806973221 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -2416,3 +2416,6 @@ DEF_HELPER_FLAGS_5(sve2_uabal_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_uabal_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_5(sve2_adcl_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve2_adcl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 6cf09847a0..f4f0c2ade6 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1247,3 +1247,9 @@ SABALB 01000101 .. 0 ..... 1100 00 ..... .....
@rda_rn_rm
SABALT 01000101 .. 0 ..... 1100 01 ..... ..... @rda_rn_rm
UABALB 01000101 .. 0 ..... 1100 10 ..... ..... @rda_rn_rm
UABALT 01000101 .. 0 ..... 1100 11 ..... ..... @rda_rn_rm
+
+## SVE2 integer add/subtract long with carry
+
+# ADC and SBC decoded via size in helper dispatch.
+ADCLB 01000101 .. 0 ..... 11010 0 ..... ..... @rda_rn_rm
+ADCLT 01000101 .. 0 ..... 11010 1 ..... ..... @rda_rn_rm
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index cc8450c44e..a7ba9e71d5 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -1264,6 +1264,40 @@ DO_ZZZW_ACC(sve2_uabal_d, uint64_t, uint32_t, ,
H1_4, DO_ABD)
#undef DO_ZZZW_ACC
+void HELPER(sve2_adcl_s)(void *vd, void *vn, void *vm, void *va, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc);
+ int sel = H4(extract32(desc, SIMD_DATA_SHIFT, 1));
+ uint32_t inv = -extract32(desc, SIMD_DATA_SHIFT + 1, 1);
+ uint32_t *a = va, *n = vn;
+ uint64_t *d = vd, *m = vm;
+
+ for (i = 0; i < opr_sz / 8; ++i) {
+ uint32_t e1 = a[2 * i + H4(0)];
+ uint32_t e2 = n[2 * i + sel] ^ inv;
+ uint64_t c = extract64(m[i], 32, 1);
+ /* Compute and store the entire 33-bit result at once. */
+ d[i] = c + e1 + e2;
+ }
+}
+
+void HELPER(sve2_adcl_d)(void *vd, void *vn, void *vm, void *va, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc);
+ int sel = extract32(desc, SIMD_DATA_SHIFT, 1);
+ uint64_t inv = -(uint64_t)extract32(desc, SIMD_DATA_SHIFT + 1, 1);
+ uint64_t *d = vd, *a = va, *n = vn, *m = vm;
+
+ for (i = 0; i < opr_sz / 8; i += 2) {
+ Int128 e1 = int128_make64(a[i]);
+ Int128 e2 = int128_make64(n[i + sel] ^ inv);
+ Int128 c = int128_make64(m[i + 1] & 1);
+ Int128 r = int128_add(int128_add(e1, e2), c);
+ d[i + 0] = int128_getlo(r);
+ d[i + 1] = int128_gethi(r);
+ }
+}
+
#define DO_BITPERM(NAME, TYPE, OP) \
void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
{ \
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 7b3720e8ef..4e23b6cedd 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -6381,3 +6381,26 @@ static bool trans_UABALT(DisasContext *s, arg_rrrr_esz
*a)
{
return do_abal(s, a, true, true);
}
+
+static bool do_adcl(DisasContext *s, arg_rrrr_esz *a, bool sel)
+{
+ static gen_helper_gvec_4 * const fns[2] = {
+ gen_helper_sve2_adcl_s,
+ gen_helper_sve2_adcl_d,
+ };
+ /*
+ * Note that in this case the ESZ field encodes both size and sign.
+ * Split out 'subtract' into bit 1 of the data field for the helper.
+ */
+ return do_sve2_zzzz_ool(s, a, fns[a->esz & 1], (a->esz & 2) | sel);
+}
+
+static bool trans_ADCLB(DisasContext *s, arg_rrrr_esz *a)
+{
+ return do_adcl(s, a, false);
+}
+
+static bool trans_ADCLT(DisasContext *s, arg_rrrr_esz *a)
+{
+ return do_adcl(s, a, true);
+}
--
2.25.1
- [PATCH v3 14/81] target/arm: Implement SVE2 integer add/subtract interleaved long, (continued)
- [PATCH v3 14/81] target/arm: Implement SVE2 integer add/subtract interleaved long, Richard Henderson, 2020/09/18
- [PATCH v3 12/81] target/arm: Implement SVE2 saturating add/subtract (predicated), Richard Henderson, 2020/09/18
- [PATCH v3 17/81] target/arm: Implement PMULLB and PMULLT, Richard Henderson, 2020/09/18
- [PATCH v3 15/81] target/arm: Implement SVE2 integer add/subtract wide, Richard Henderson, 2020/09/18
- [PATCH v3 18/81] target/arm: Implement SVE2 bitwise shift left long, Richard Henderson, 2020/09/18
- [PATCH v3 16/81] target/arm: Implement SVE2 integer multiply long, Richard Henderson, 2020/09/18
- [PATCH v3 19/81] target/arm: Implement SVE2 bitwise exclusive-or interleaved, Richard Henderson, 2020/09/18
- [PATCH v3 21/81] target/arm: Implement SVE2 complex integer add, Richard Henderson, 2020/09/18
- [PATCH v3 20/81] target/arm: Implement SVE2 bitwise permute, Richard Henderson, 2020/09/18
- [PATCH v3 22/81] target/arm: Implement SVE2 integer absolute difference and accumulate long, Richard Henderson, 2020/09/18
- [PATCH v3 23/81] target/arm: Implement SVE2 integer add/subtract long with carry,
Richard Henderson <=
- [PATCH v3 24/81] target/arm: Implement SVE2 bitwise shift right and accumulate, Richard Henderson, 2020/09/18
- [PATCH v3 25/81] target/arm: Implement SVE2 bitwise shift and insert, Richard Henderson, 2020/09/18
- [PATCH v3 26/81] target/arm: Implement SVE2 integer absolute difference and accumulate, Richard Henderson, 2020/09/18
- [PATCH v3 27/81] target/arm: Implement SVE2 saturating extract narrow, Richard Henderson, 2020/09/18
- [PATCH v3 28/81] target/arm: Implement SVE2 floating-point pairwise, Richard Henderson, 2020/09/18
- [PATCH v3 29/81] target/arm: Implement SVE2 SHRN, RSHRN, Richard Henderson, 2020/09/18
- [PATCH v3 30/81] target/arm: Implement SVE2 SQSHRUN, SQRSHRUN, Richard Henderson, 2020/09/18
- [PATCH v3 31/81] target/arm: Implement SVE2 UQSHRN, UQRSHRN, Richard Henderson, 2020/09/18
- [PATCH v3 33/81] target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS, Richard Henderson, 2020/09/18
- [PATCH v3 32/81] target/arm: Implement SVE2 SQSHRN, SQRSHRN, Richard Henderson, 2020/09/18