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Re: [PATCH v5 06/11] riscv: Initial commit of OpenTitan machine
From: |
Peter Maydell |
Subject: |
Re: [PATCH v5 06/11] riscv: Initial commit of OpenTitan machine |
Date: |
Wed, 9 Sep 2020 20:00:07 +0100 |
On Wed, 9 Sep 2020 at 19:00, Alistair Francis <alistair23@gmail.com> wrote:
>
> On Tue, Sep 8, 2020 at 7:52 AM Peter Maydell <peter.maydell@linaro.org> wrote:
> > ...shouldn't the riscv64-softmmu config have CONFIG_OPENTITAN too?
> > The usual principle is that the 64-bit executable can run the
> > 32-bit boards too.
>
> I didn't know that was the general case. I'll send a patch to enable this.
Somebody on IRC suggested that the riscv code currently
assumes that #ifdef TARGET_RISCV64 implies a 64-bit CPU,
ie that the 32-bit CPUs don't actually behave correctly
if built into the qemu-system-riscv64 process, so you might
want to check that things seem to work when you enable it...
thanks
-- pMM