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[PATCH 0/3] target/arm: Decode Neon fp sizes in decodetree

From: Peter Maydell
Subject: [PATCH 0/3] target/arm: Decode Neon fp sizes in decodetree
Date: Thu, 3 Sep 2020 14:32:06 +0100

This patchset fixes something that Richard pointed out during
review of my fp16 patchset.

In the Neon instruction set, integer operations always have a 2-bit
size field with an encoding corresponding to QEMU's MO_{8,16,32,64}
constants: 0 for 8 bit, 1 for 16 bit, 2 for 32 bit and 3 for 64-bit.
However for the floating point instructions, since only 16-bit
and 32-bit floats are supported some instructions use one of the
size bits as part of decode, leaving only a 1-bit size field,
which might be encoded either as 0 for 16-bit float and 1 for
32-bit float, or the other way around as 0 for 32-bit float and
1 for 16-bit float.

Currently we simply pass the raw size field values through from
decodetree to the trans_ functions, which means that when reading
or writing the code for a trans_ function you need to know the
encoding of the size field for that insn. This patchset moves
the handling of the different possible encodings into the decodetree
file, so that the trans_ function is always passed a MO_* value
for the size.

-- PMM

Peter Maydell (3):
  target/arm: Convert Neon 3-same-fp size field to MO_* in decode
  target/arm: Convert Neon VCVT fp size field to MO_* in decode
  target/arm: Convert VCMLA, VCADD size field to MO_* in decode

 target/arm/neon-dp.decode       | 18 ++++++++------
 target/arm/neon-shared.decode   | 18 +++++++++-----
 target/arm/translate-neon.c.inc | 42 ++++++++++++++++++++-------------
 3 files changed, 48 insertions(+), 30 deletions(-)


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