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Re: [PATCH v2 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit bo
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From: |
Bin Meng |
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Subject: |
Re: [PATCH v2 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support |
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Date: |
Mon, 31 Aug 2020 06:15:52 +0800 |
Hi Leif,
On Sun, Aug 30, 2020 at 8:57 PM Leif Lindholm <leif@nuviainc.com> wrote:
>
> Hi Bin,
>
> On Sat, Aug 29, 2020 at 23:17:24 +0800, Bin Meng wrote:
> > From: Bin Meng <bin.meng@windriver.com>
> >
> > This adds support for Microchip PolarFire SoC Icicle Kit board.
> > The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
> > E51 plus four U54 cores and many on-chip peripherals and an FPGA.
> >
> > For more details about Microchip PolarFire SoC, please see:
> > https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
> >
> > The Icicle Kit board information can be found here:
> > https://www.microsemi.com/existing-parts/parts/152514
> >
> > Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000.
> > The RISC-V CPU and HART codes has been updated to set the core's
> > reset vector based on a configurable property from machine codes.
> >
> > The following perepherals are created as an unimplemented device:
> >
> > - Bus Error Uint 0/1/2/3/4
> > - L2 cache controller
> > - SYSREG
> > - MPUCFG
> > - IOSCBCFG
> > - GPIO
> >
> > The following perepherals are emulated:
> > - SiFive CLINT
> > - SiFive PLIC
> > - PolarFire SoC Multi-Mode UART
> > - SiFive PDMA
> > - Cadence eMMC/SDHCI controller
> > - Cadence Gigabit Ethernet MAC
> >
> > The BIOS image used by this machine is hss.bin, aka Hart Software
> > Services, which can be built from:
> > https://github.com/polarfire-soc/hart-software-services
>
> Are there any version requirements, or additional qemu patches, that
> need to be taken into account. Should I expect to see output on stdio?
Thanks for trying!
Did you apply the patch to skip the DDR memory initialization
mentioned in this page?
https://wiki.qemu.org/Documentation/Platforms/RISCV#Microchip_PolarFire_SoC_Icicle_Kit
>
> I tried to build hss 3faaaaf8ce0d, using
> https://github.com/riscv/riscv-gnu-toolchain (7f1f4ab5b0e0), which
> ends up being a gcc 10.1. That caused me to raise
> https://github.com/polarfire-soc/hart-software-services/issues/2.
Yes, GCC 10 does not build is a known issue. Currently I am using GCC
9 to build HSS.
>
> Suppressing that warning gets me a hss.bin, but neither that, nor one
> I build with Debian's 8.3 riscv64-linux-gnu- produces any output when
> I apply this set on top of 39335fab59. (Even when I change the wait to
> nowait.)
>
Regards,
Bin
- [PATCH v2 08/16] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card, (continued)
- [PATCH v2 08/16] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card, Bin Meng, 2020/08/29
- [PATCH v2 09/16] hw/dma: Add SiFive platform DMA controller emulation, Bin Meng, 2020/08/29
- [PATCH v2 10/16] hw/riscv: microchip_pfsoc: Connect a DMA controller, Bin Meng, 2020/08/29
- [PATCH v2 11/16] hw/net: cadence_gem: Add a new 'phy-addr' property, Bin Meng, 2020/08/29
- [PATCH v2 12/16] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23, Bin Meng, 2020/08/29
- [PATCH v2 13/16] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs, Bin Meng, 2020/08/29
- [PATCH v2 14/16] hw/riscv: microchip_pfsoc: Hook GPIO controllers, Bin Meng, 2020/08/29
- [PATCH v2 15/16] hw/riscv: clint: Avoid using hard-coded timebase frequency, Bin Meng, 2020/08/29
- [PATCH v2 16/16] hw/riscv: sifive_u: Connect a DMA controller, Bin Meng, 2020/08/29
- Re: [PATCH v2 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support, Leif Lindholm, 2020/08/30
- Re: [PATCH v2 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support,
Bin Meng <=