[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [RFC v4 12/70] target/riscv: rvv-1.0: add fractional LMUL
|
From: |
Richard Henderson |
|
Subject: |
Re: [RFC v4 12/70] target/riscv: rvv-1.0: add fractional LMUL |
|
Date: |
Sat, 29 Aug 2020 08:51:51 -0700 |
|
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 8/17/20 1:48 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> Introduce the concepts of fractional LMUL for RVV 1.0.
> In RVV 1.0, LMUL bits are contiguous in vtype register.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/cpu.h | 15 ++++++++-------
> target/riscv/translate.c | 16 ++++++++++++++--
> target/riscv/vector_helper.c | 16 ++++++++++++++--
> 3 files changed, 36 insertions(+), 11 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
- [RFC v4 03/70] target/riscv: rvv-1.0: add mstatus VS field, (continued)
- [RFC v4 03/70] target/riscv: rvv-1.0: add mstatus VS field, frank . chang, 2020/08/17
- [RFC v4 04/70] target/riscv: rvv-1.0: add sstatus VS field, frank . chang, 2020/08/17
- [RFC v4 05/70] target/riscv: rvv-1.0: introduce writable misa.v field, frank . chang, 2020/08/17
- [RFC v4 06/70] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2020/08/17
- [RFC v4 07/70] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers, frank . chang, 2020/08/17
- [RFC v4 08/70] target/riscv: rvv-1.0: add vcsr register, frank . chang, 2020/08/17
- [RFC v4 09/70] target/riscv: rvv-1.0: add vlenb register, frank . chang, 2020/08/17
- [RFC v4 10/70] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, frank . chang, 2020/08/17
- [RFC v4 12/70] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 2020/08/17
- Re: [RFC v4 12/70] target/riscv: rvv-1.0: add fractional LMUL,
Richard Henderson <=
- [RFC v4 11/70] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2020/08/17
- [RFC v4 13/70] target/riscv: rvv-1.0: add VMA and VTA, frank . chang, 2020/08/17
- [RFC v4 15/70] target/riscv: introduce more imm value modes in translator functions, frank . chang, 2020/08/17
- [RFC v4 14/70] target/riscv: rvv-1.0: update check functions, frank . chang, 2020/08/17
- [RFC v4 16/70] target/riscv: rvv:1.0: add translation-time nan-box helper function, frank . chang, 2020/08/17
- [RFC v4 17/70] target/riscv: rvv-1.0: configure instructions, frank . chang, 2020/08/17
- [RFC v4 18/70] target/riscv: rvv-1.0: stride load and store instructions, frank . chang, 2020/08/17