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[PATCH v2 06/76] target/microblaze: Split out MSR from env->sregs
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From: |
Richard Henderson |
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Subject: |
[PATCH v2 06/76] target/microblaze: Split out MSR from env->sregs |
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Date: |
Fri, 28 Aug 2020 07:18:19 -0700 |
Continue eliminating the sregs array in favor of individual members.
Does not correct the width of MSR, yet.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/microblaze/cpu.h | 7 ++---
target/microblaze/cpu.c | 4 +--
target/microblaze/gdbstub.c | 4 +--
target/microblaze/helper.c | 49 +++++++++++++++++------------------
target/microblaze/op_helper.c | 22 ++++++++--------
target/microblaze/translate.c | 14 +++++-----
6 files changed, 51 insertions(+), 49 deletions(-)
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index d1f91bb318..36de61d9f9 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -237,6 +237,7 @@ struct CPUMBState {
uint32_t imm;
uint32_t regs[32];
uint64_t pc;
+ uint64_t msr;
uint64_t sregs[14];
float_status fp_status;
/* Stack protectors. Yes, it's a hw feature. */
@@ -355,7 +356,7 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *env,
target_ulong *pc,
*pc = env->pc;
*cs_base = 0;
*flags = (env->iflags & IFLAGS_TB_MASK) |
- (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE));
+ (env->msr & (MSR_UM | MSR_VM | MSR_EE));
}
#if !defined(CONFIG_USER_ONLY)
@@ -370,11 +371,11 @@ static inline int cpu_mmu_index(CPUMBState *env, bool
ifetch)
MicroBlazeCPU *cpu = env_archcpu(env);
/* Are we in nommu mode?. */
- if (!(env->sregs[SR_MSR] & MSR_VM) || !cpu->cfg.use_mmu) {
+ if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) {
return MMU_NOMMU_IDX;
}
- if (env->sregs[SR_MSR] & MSR_UM) {
+ if (env->msr & MSR_UM) {
return MMU_USER_IDX;
}
return MMU_KERNEL_IDX;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index bde9992535..0eac068570 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -121,9 +121,9 @@ static void mb_cpu_reset(DeviceState *dev)
#if defined(CONFIG_USER_ONLY)
/* start in user mode with interrupts enabled. */
- env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
+ env->msr = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
#else
- env->sregs[SR_MSR] = 0;
+ env->msr = 0;
mmu_init(&env->mmu);
env->mmu.c_mmu = 3;
env->mmu.c_mmu_tlb_access = 3;
diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c
index 9ea31f8d2f..e4c4936a7a 100644
--- a/target/microblaze/gdbstub.c
+++ b/target/microblaze/gdbstub.c
@@ -62,7 +62,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray
*mem_buf, int n)
val = env->pc;
break;
case GDB_MSR:
- val = env->sregs[SR_MSR];
+ val = env->msr;
break;
case GDB_EAR:
val = env->sregs[SR_EAR];
@@ -118,7 +118,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t
*mem_buf, int n)
env->pc = tmp;
break;
case GDB_MSR:
- env->sregs[SR_MSR] = tmp;
+ env->msr = tmp;
break;
case GDB_EAR:
env->sregs[SR_EAR] = tmp;
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index 5c392deea4..a18314540f 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -117,7 +117,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
/* IMM flag cannot propagate across a branch and into the dslot. */
assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG)));
assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)));
-/* assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions. */
+/* assert(env->msr & (MSR_EE)); Only for HW exceptions. */
env->res_addr = RES_ADDR_NONE;
switch (cs->exception_index) {
case EXCP_HW_EXCP:
@@ -136,11 +136,11 @@ void mb_cpu_do_interrupt(CPUState *cs)
}
/* Disable the MMU. */
- t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
- env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
- env->sregs[SR_MSR] |= t;
+ t = (env->msr & (MSR_VM | MSR_UM)) << 1;
+ env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
+ env->msr |= t;
/* Exception in progress. */
- env->sregs[SR_MSR] |= MSR_EIP;
+ env->msr |= MSR_EIP;
qemu_log_mask(CPU_LOG_INT,
"hw exception at pc=%" PRIx64 " ear=%" PRIx64 " "
@@ -179,11 +179,11 @@ void mb_cpu_do_interrupt(CPUState *cs)
}
/* Disable the MMU. */
- t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
- env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
- env->sregs[SR_MSR] |= t;
+ t = (env->msr & (MSR_VM | MSR_UM)) << 1;
+ env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
+ env->msr |= t;
/* Exception in progress. */
- env->sregs[SR_MSR] |= MSR_EIP;
+ env->msr |= MSR_EIP;
qemu_log_mask(CPU_LOG_INT,
"exception at pc=%" PRIx64 " ear=%" PRIx64 " "
@@ -195,11 +195,11 @@ void mb_cpu_do_interrupt(CPUState *cs)
break;
case EXCP_IRQ:
- assert(!(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)));
- assert(env->sregs[SR_MSR] & MSR_IE);
+ assert(!(env->msr & (MSR_EIP | MSR_BIP)));
+ assert(env->msr & MSR_IE);
assert(!(env->iflags & D_FLAG));
- t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
+ t = (env->msr & (MSR_VM | MSR_UM)) << 1;
#if 0
#include "disas/disas.h"
@@ -216,7 +216,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
qemu_log(
"interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n",
- env->pc, env->sregs[SR_MSR], t, env->iflags,
+ env->pc, env->msr, t, env->iflags,
sym);
log_cpu_state(cs, 0);
@@ -226,11 +226,10 @@ void mb_cpu_do_interrupt(CPUState *cs)
qemu_log_mask(CPU_LOG_INT,
"interrupt at pc=%" PRIx64 " msr=%" PRIx64 " %x "
"iflags=%x\n",
- env->pc, env->sregs[SR_MSR], t, env->iflags);
+ env->pc, env->msr, t, env->iflags);
- env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \
- | MSR_UM | MSR_IE);
- env->sregs[SR_MSR] |= t;
+ env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE);
+ env->msr |= t;
env->regs[14] = env->pc;
env->pc = cpu->cfg.base_vectors + 0x10;
@@ -241,18 +240,18 @@ void mb_cpu_do_interrupt(CPUState *cs)
case EXCP_HW_BREAK:
assert(!(env->iflags & IMM_FLAG));
assert(!(env->iflags & D_FLAG));
- t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
+ t = (env->msr & (MSR_VM | MSR_UM)) << 1;
qemu_log_mask(CPU_LOG_INT,
"break at pc=%" PRIx64 " msr=%" PRIx64 " %x "
"iflags=%x\n",
- env->pc, env->sregs[SR_MSR], t, env->iflags);
+ env->pc, env->msr, t, env->iflags);
log_cpu_state_mask(CPU_LOG_INT, cs, 0);
- env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
- env->sregs[SR_MSR] |= t;
- env->sregs[SR_MSR] |= MSR_BIP;
+ env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
+ env->msr |= t;
+ env->msr |= MSR_BIP;
if (cs->exception_index == EXCP_HW_BREAK) {
env->regs[16] = env->pc;
- env->sregs[SR_MSR] |= MSR_BIP;
+ env->msr |= MSR_BIP;
env->pc = cpu->cfg.base_vectors + 0x18;
} else
env->pc = env->btarget;
@@ -293,8 +292,8 @@ bool mb_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
CPUMBState *env = &cpu->env;
if ((interrupt_request & CPU_INTERRUPT_HARD)
- && (env->sregs[SR_MSR] & MSR_IE)
- && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
+ && (env->msr & MSR_IE)
+ && !(env->msr & (MSR_EIP | MSR_BIP))
&& !(env->iflags & (D_FLAG | IMM_FLAG))) {
cs->exception_index = EXCP_IRQ;
mb_cpu_do_interrupt(cs);
diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
index 2deef32740..3668382d36 100644
--- a/target/microblaze/op_helper.c
+++ b/target/microblaze/op_helper.c
@@ -78,14 +78,14 @@ void helper_debug(CPUMBState *env)
qemu_log("PC=%" PRIx64 "\n", env->pc);
qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " "
"debug[%x] imm=%x iflags=%x\n",
- env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
+ env->msr, env->sregs[SR_ESR], env->sregs[SR_EAR],
env->debug, env->imm, env->iflags);
qemu_log("btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) eip=%d ie=%d\n",
env->btaken, env->btarget,
- (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
- (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
- (bool)(env->sregs[SR_MSR] & MSR_EIP),
- (bool)(env->sregs[SR_MSR] & MSR_IE));
+ (env->msr & MSR_UM) ? "user" : "kernel",
+ (env->msr & MSR_UMS) ? "user" : "kernel",
+ (bool)(env->msr & MSR_EIP),
+ (bool)(env->msr & MSR_IE));
for (i = 0; i < 32; i++) {
qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
if ((i + 1) % 4 == 0)
@@ -135,15 +135,15 @@ static inline int div_prepare(CPUMBState *env, uint32_t
a, uint32_t b)
MicroBlazeCPU *cpu = env_archcpu(env);
if (b == 0) {
- env->sregs[SR_MSR] |= MSR_DZ;
+ env->msr |= MSR_DZ;
- if ((env->sregs[SR_MSR] & MSR_EE) && cpu->cfg.div_zero_exception) {
+ if ((env->msr & MSR_EE) && cpu->cfg.div_zero_exception) {
env->sregs[SR_ESR] = ESR_EC_DIVZERO;
helper_raise_exception(env, EXCP_HW_EXCP);
}
return 0;
}
- env->sregs[SR_MSR] &= ~MSR_DZ;
+ env->msr &= ~MSR_DZ;
return 1;
}
@@ -192,7 +192,7 @@ static void update_fpu_flags(CPUMBState *env, int flags)
}
if (raise
&& (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
- && (env->sregs[SR_MSR] & MSR_EE)) {
+ && (env->msr & MSR_EE)) {
raise_fpu_exception(env);
}
}
@@ -437,7 +437,7 @@ void helper_memalign(CPUMBState *env, target_ulong addr,
if (mask == 3) {
env->sregs[SR_ESR] |= 1 << 11;
}
- if (!(env->sregs[SR_MSR] & MSR_EE)) {
+ if (!(env->msr & MSR_EE)) {
return;
}
helper_raise_exception(env, EXCP_HW_EXCP);
@@ -484,7 +484,7 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr
physaddr, vaddr addr,
env = &cpu->env;
cpu_restore_state(cs, retaddr, true);
- if (!(env->sregs[SR_MSR] & MSR_EE)) {
+ if (!(env->msr & MSR_EE)) {
return;
}
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 9f6815cc1f..9f2dcd82cd 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1809,16 +1809,16 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " "
"debug=%x imm=%x iflags=%x fsr=%" PRIx64 " "
"rbtr=%" PRIx64 "\n",
- env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
+ env->msr, env->sregs[SR_ESR], env->sregs[SR_EAR],
env->debug, env->imm, env->iflags, env->sregs[SR_FSR],
env->sregs[SR_BTR]);
qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) "
"eip=%d ie=%d\n",
env->btaken, env->btarget,
- (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
- (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
- (bool)(env->sregs[SR_MSR] & MSR_EIP),
- (bool)(env->sregs[SR_MSR] & MSR_IE));
+ (env->msr & MSR_UM) ? "user" : "kernel",
+ (env->msr & MSR_UMS) ? "user" : "kernel",
+ (bool)(env->msr & MSR_EIP),
+ (bool)(env->msr & MSR_IE));
for (i = 0; i < 12; i++) {
qemu_fprintf(f, "rpvr%2.2d=%8.8x ", i, env->pvr.regs[i]);
if ((i + 1) % 4 == 0) {
@@ -1871,8 +1871,10 @@ void mb_tcg_init(void)
cpu_SR[SR_PC] =
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc");
+ cpu_SR[SR_MSR] =
+ tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr");
- for (i = 1; i < ARRAY_SIZE(cpu_SR); i++) {
+ for (i = SR_MSR + 1; i < ARRAY_SIZE(cpu_SR); i++) {
cpu_SR[i] = tcg_global_mem_new_i64(cpu_env,
offsetof(CPUMBState, sregs[i]),
special_regnames[i]);
--
2.25.1
- [PATCH v2 00/76] target/microblaze improvements, Richard Henderson, 2020/08/28
- [PATCH v2 01/76] tests/tcg: Add microblaze to arches filter, Richard Henderson, 2020/08/28
- [PATCH v2 02/76] tests/tcg: Do not require FE_TOWARDZERO, Richard Henderson, 2020/08/28
- [PATCH v2 03/76] tests/tcg: Do not require FE_* exception bits, Richard Henderson, 2020/08/28
- [PATCH v2 04/76] target/microblaze: Tidy gdbstub, Richard Henderson, 2020/08/28
- [PATCH v2 05/76] target/microblaze: Split out PC from env->sregs, Richard Henderson, 2020/08/28
- [PATCH v2 06/76] target/microblaze: Split out MSR from env->sregs,
Richard Henderson <=
- [PATCH v2 07/76] target/microblaze: Split out EAR from env->sregs, Richard Henderson, 2020/08/28
- [PATCH v2 08/76] target/microblaze: Split out ESR from env->sregs, Richard Henderson, 2020/08/28
- [PATCH v2 09/76] target/microblaze: Split out FSR from env->sregs, Richard Henderson, 2020/08/28
- [PATCH v2 10/76] target/microblaze: Split out BTR from env->sregs, Richard Henderson, 2020/08/28
- [PATCH v2 11/76] target/microblaze: Split out EDR from env->sregs, Richard Henderson, 2020/08/28
- [PATCH v2 12/76] target/microblaze: Split the cpu_SR array, Richard Henderson, 2020/08/28
- [PATCH v2 13/76] target/microblaze: Fix width of PC and BTARGET, Richard Henderson, 2020/08/28