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[PULL 01/27] hw/cpu/a9mpcore: Verify the machine use Cortex-A9 cores
From: |
Peter Maydell |
Subject: |
[PULL 01/27] hw/cpu/a9mpcore: Verify the machine use Cortex-A9 cores |
Date: |
Mon, 24 Aug 2020 10:47:45 +0100 |
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
The 'Cortex-A9MPCore internal peripheral' block can only be
used with Cortex A5 and A9 cores. As we don't model the A5
yet, simply check the machine cpu core is a Cortex A9. If
not return an error.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200709152337.15533-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/cpu/a9mpcore.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index 351295e5187..ec186d49abd 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -15,6 +15,7 @@
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/core/cpu.h"
+#include "cpu.h"
#define A9_GIC_NUM_PRIORITY_BITS 5
@@ -52,8 +53,18 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
*wdtbusdev;
int i;
bool has_el3;
+ CPUState *cpu0;
Object *cpuobj;
+ cpu0 = qemu_get_cpu(0);
+ cpuobj = OBJECT(cpu0);
+ if (strcmp(object_get_typename(cpuobj), ARM_CPU_TYPE_NAME("cortex-a9"))) {
+ /* We might allow Cortex-A5 once we model it */
+ error_setg(errp,
+ "Cortex-A9MPCore peripheral can only use Cortex-A9 CPU");
+ return;
+ }
+
scudev = DEVICE(&s->scu);
qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
@@ -70,7 +81,6 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
/* Make the GIC's TZ support match the CPUs. We assume that
* either all the CPUs have TZ, or none do.
*/
- cpuobj = OBJECT(qemu_get_cpu(0));
has_el3 = object_property_find(cpuobj, "has_el3", NULL) &&
object_property_get_bool(cpuobj, "has_el3", &error_abort);
qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
--
2.20.1
- [PULL 00/27] target-arm queue, Peter Maydell, 2020/08/24
- [PULL 01/27] hw/cpu/a9mpcore: Verify the machine use Cortex-A9 cores,
Peter Maydell <=
- [PULL 02/27] hw/arm/smmu-common: Factorize some code in smmu_ptw_64(), Peter Maydell, 2020/08/24
- [PULL 04/27] hw/arm/smmu: Introduce smmu_get_iotlb_key(), Peter Maydell, 2020/08/24
- [PULL 03/27] hw/arm/smmu-common: Add IOTLB helpers, Peter Maydell, 2020/08/24
- [PULL 05/27] hw/arm/smmu: Introduce SMMUTLBEntry for PTW and IOTLB value, Peter Maydell, 2020/08/24
- [PULL 06/27] hw/arm/smmu-common: Manage IOTLB block entries, Peter Maydell, 2020/08/24
- [PULL 07/27] hw/arm/smmuv3: Introduce smmuv3_s1_range_inval() helper, Peter Maydell, 2020/08/24
- [PULL 08/27] hw/arm/smmuv3: Get prepared for range invalidation, Peter Maydell, 2020/08/24
- [PULL 09/27] hw/arm/smmuv3: Fix IIDR offset, Peter Maydell, 2020/08/24
- [PULL 10/27] hw/arm/smmuv3: Let AIDR advertise SMMUv3.0 support, Peter Maydell, 2020/08/24
- [PULL 11/27] hw/arm/smmuv3: Support HAD and advertise SMMUv3.1 support, Peter Maydell, 2020/08/24