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Re: [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board
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From: |
Cyril.Jean |
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Subject: |
Re: [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support |
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Date: |
Mon, 17 Aug 2020 15:44:06 +0000 |
Hi Anup,
On 8/17/20 11:30 AM, Bin Meng wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
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>
> Hi Anup,
>
> On Sat, Aug 15, 2020 at 1:44 AM Anup Patel <anup@brainfault.org> wrote:
>> On Fri, Aug 14, 2020 at 10:12 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>>> From: Bin Meng <bin.meng@windriver.com>
>>>
>>> This adds support for Microchip PolarFire SoC Icicle Kit board.
>>> The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
>>> E51 plus four U54 cores and many on-chip peripherals and an FPGA.
>> Nice Work !!! This is very helpful.
> Thanks!
>
>> The Microchip HSS is quite convoluted. It has:
>> 1. DDR Init
>> 2. Boot device support
>> 3. SBI support using OpenSBI as library
>> 4. Simple TEE support
>>
>> I think point 1) and 2) above should be part of U-Boot SPL.
>> The point 3) can be OpenSBI FW_DYNAMIC.
>>
>> Lastly,for point 4), we are working on a new OpenSBI feature using
>> which we can run independent Secure OS and Non-Secure OS using
>> U-Boot_SPL+OpenSBI (for both SiFive Unleashed and Microchip
>> PolarFire).
>>
>> Do you have plans for adding U-Boot SPL support for this board ??
> + Cyril Jean from Microchip
>
> I will have to leave this question to Cyril to comment.
>
I currently do not have a plan to support U-Boot SPL. The idea of the
HSS is to contain all the silicon specific initialization and
configuration code within the HSS before jumping to U-Boot S-mode. I
would rather keep all this within the HSS for the time being. I would
wait until we reach production silicon before attempting to move this to
U-Boot SPL as the HSS is likely to contain some opaque silicon related
changes for another while.
Regards,
Cyril.
- [PATCH 15/18] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs, (continued)
- [PATCH 15/18] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs, Bin Meng, 2020/08/14
- [PATCH 16/18] hw/riscv: microchip_pfsoc: Hook GPIO controllers, Bin Meng, 2020/08/14
- [PATCH 17/18] hw/riscv: clint: Avoid using hard-coded timebase frequency, Bin Meng, 2020/08/14
- [PATCH 18/18] hw/riscv: microchip_pfsoc: Document the software used for testing, Bin Meng, 2020/08/14
- Re: [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support, Anup Patel, 2020/08/14
- Re: [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support, Bin Meng, 2020/08/17
- Re: [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support,
Cyril.Jean <=
- Re: [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support, Alistair Francis, 2020/08/17
- Re: [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support, Cyril.Jean, 2020/08/17
- Re: [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support, Anup Patel, 2020/08/18
- Re: [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support, Cyril.Jean, 2020/08/18
- Re: [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support, Anup Patel, 2020/08/18
- Re: [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support, Bin Meng, 2020/08/18
- Re: [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support, Cyril.Jean, 2020/08/19
- Re: [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support, Alistair Francis, 2020/08/21
Re: [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support, no-reply, 2020/08/14