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[RFC v4 39/70] target/riscv: rvv-1.0: integer extension instructions
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From: |
frank . chang |
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Subject: |
[RFC v4 39/70] target/riscv: rvv-1.0: integer extension instructions |
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Date: |
Mon, 17 Aug 2020 16:49:24 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Add the following instructions:
* vzext.vf2
* vzext.vf4
* vzext.vf8
* vsext.vf2
* vsext.vf4
* vsext.vf8
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/helper.h | 14 ++++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 86 +++++++++++++++++++++++++
target/riscv/vector_helper.c | 31 +++++++++
4 files changed, 139 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 35fb09d2892..7ce2fa08d58 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1118,3 +1118,17 @@ DEF_HELPER_6(vcompress_vm_b, void, ptr, ptr, ptr, ptr,
env, i32)
DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_5(vzext_vf2_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vzext_vf2_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vzext_vf2_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vzext_vf4_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vzext_vf4_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vzext_vf8_d, void, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_5(vsext_vf2_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vsext_vf2_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vsext_vf2_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vsext_vf4_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vsext_vf4_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vsext_vf8_d, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 65ff1688c25..2b9700a42ad 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -619,5 +619,13 @@ vmv2r_v 100111 1 ..... 00001 011 ..... 1010111
@r2rd
vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd
vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd
+# Vector Integer Extension
+vzext_vf2 010010 . ..... 00110 010 ..... 1010111 @r2_vm
+vzext_vf4 010010 . ..... 00100 010 ..... 1010111 @r2_vm
+vzext_vf8 010010 . ..... 00010 010 ..... 1010111 @r2_vm
+vsext_vf2 010010 . ..... 00111 010 ..... 1010111 @r2_vm
+vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm
+vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm
+
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 52f2f4902c0..5cd099bed7b 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -3504,3 +3504,89 @@ GEN_VMV_WHOLE_TRANS(vmv1r_v, 1)
GEN_VMV_WHOLE_TRANS(vmv2r_v, 2)
GEN_VMV_WHOLE_TRANS(vmv4r_v, 4)
GEN_VMV_WHOLE_TRANS(vmv8r_v, 8)
+
+static bool int_ext_check(DisasContext *s, arg_rmr *a, uint8_t div)
+{
+ uint8_t from = (s->sew + 3) - div;
+ bool ret = require_rvv(s);
+ ret &= (from >= 3 && from <= 8) &&
+ (a->rd != a->rs2) &&
+ require_align(a->rd, 1 << s->lmul) &&
+ require_align(a->rs2, 1 << (s->lmul - div)) &&
+ require_vm(a->vm, a->rd);
+ if ((s->lmul - div) < 0) {
+ ret &= require_noover(a->rd, 1 << s->lmul,
+ a->rs2, 1 << (s->lmul - div));
+ } else {
+ ret &= require_noover_widen(a->rd, 1 << s->lmul, a->rs2,
+ 1 << (s->lmul - div));
+ }
+ return ret;
+}
+
+static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
+{
+ uint32_t data = 0;
+ gen_helper_gvec_3_ptr *fn;
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ static gen_helper_gvec_3_ptr * const fns[6][4] = {
+ {
+ NULL, gen_helper_vzext_vf2_h,
+ gen_helper_vzext_vf2_w, gen_helper_vzext_vf2_d
+ },
+ {
+ NULL, NULL,
+ gen_helper_vzext_vf4_w, gen_helper_vzext_vf4_d,
+ },
+ {
+ NULL, NULL,
+ NULL, gen_helper_vzext_vf8_d
+ },
+ {
+ NULL, gen_helper_vsext_vf2_h,
+ gen_helper_vsext_vf2_w, gen_helper_vsext_vf2_d
+ },
+ {
+ NULL, NULL,
+ gen_helper_vsext_vf4_w, gen_helper_vsext_vf4_d,
+ },
+ {
+ NULL, NULL,
+ NULL, gen_helper_vsext_vf8_d
+ }
+ };
+
+ fn = fns[seq][s->sew];
+ if (fn == NULL) {
+ return false;
+ }
+
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
+ vreg_ofs(s, a->rs2), cpu_env, 0,
+ s->vlen / 8, data, fn);
+
+ mark_vs_dirty(s);
+ gen_set_label(over);
+ return true;
+}
+
+/* Vector Integer Extension */
+#define GEN_INT_EXT_TRANS(NAME, DIV, SEQ) \
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
+{ \
+ if (int_ext_check(s, a, DIV)) { \
+ return int_ext_op(s, a, SEQ); \
+ } \
+ return false; \
+}
+
+GEN_INT_EXT_TRANS(vzext_vf2, 1, 0)
+GEN_INT_EXT_TRANS(vzext_vf4, 2, 1)
+GEN_INT_EXT_TRANS(vzext_vf8, 3, 2)
+GEN_INT_EXT_TRANS(vsext_vf2, 1, 3)
+GEN_INT_EXT_TRANS(vsext_vf4, 2, 4)
+GEN_INT_EXT_TRANS(vsext_vf8, 3, 5)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 26a8ac6fe25..ad3408888d4 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4775,3 +4775,34 @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_b, uint8_t, H1)
GEN_VEXT_VCOMPRESS_VM(vcompress_vm_h, uint16_t, H2)
GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4)
GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8)
+
+/* Vector Integer Extension */
+#define GEN_VEXT_INT_EXT(NAME, ETYPE, DTYPE, HD, HS1) \
+void HELPER(NAME)(void *vd, void *v0, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t vl = env->vl; \
+ uint32_t vm = vext_vm(desc); \
+ uint32_t i; \
+ \
+ for (i = 0; i < vl; i++) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
+ continue; \
+ } \
+ *((ETYPE *)vd + HD(i)) = *((DTYPE *)vs2 + HS1(i)); \
+ } \
+}
+
+GEN_VEXT_INT_EXT(vzext_vf2_h, uint16_t, uint8_t, H2, H1)
+GEN_VEXT_INT_EXT(vzext_vf2_w, uint32_t, uint16_t, H4, H2)
+GEN_VEXT_INT_EXT(vzext_vf2_d, uint64_t, uint32_t, H8, H4)
+GEN_VEXT_INT_EXT(vzext_vf4_w, uint32_t, uint8_t, H4, H1)
+GEN_VEXT_INT_EXT(vzext_vf4_d, uint64_t, uint16_t, H8, H2)
+GEN_VEXT_INT_EXT(vzext_vf8_d, uint64_t, uint8_t, H8, H1)
+
+GEN_VEXT_INT_EXT(vsext_vf2_h, int16_t, int8_t, H2, H1)
+GEN_VEXT_INT_EXT(vsext_vf2_w, int32_t, int16_t, H4, H2)
+GEN_VEXT_INT_EXT(vsext_vf2_d, int64_t, int32_t, H8, H4)
+GEN_VEXT_INT_EXT(vsext_vf4_w, int32_t, int8_t, H4, H1)
+GEN_VEXT_INT_EXT(vsext_vf4_d, int64_t, int16_t, H8, H2)
+GEN_VEXT_INT_EXT(vsext_vf8_d, int64_t, int8_t, H8, H1)
--
2.17.1
- [RFC v4 32/70] target/riscv: rvv-1.0: element index instruction, (continued)
- [RFC v4 32/70] target/riscv: rvv-1.0: element index instruction, frank . chang, 2020/08/17
- [RFC v4 33/70] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2020/08/17
- [RFC v4 34/70] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2020/08/17
- [RFC v4 35/70] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2020/08/17
- [RFC v4 36/70] target/riscv: rvv-1.0: floating-point move instruction, frank . chang, 2020/08/17
- [RFC v4 37/70] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 2020/08/17
- [RFC v4 39/70] target/riscv: rvv-1.0: integer extension instructions,
frank . chang <=
- [RFC v4 38/70] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 2020/08/17
- [RFC v4 42/70] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, frank . chang, 2020/08/17
- [RFC v4 43/70] target/riscv: rvv-1.0: narrowing integer right shift instructions, frank . chang, 2020/08/17
- [RFC v4 40/70] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, frank . chang, 2020/08/17
- [RFC v4 41/70] target/riscv: rvv-1.0: single-width bit shift instructions, frank . chang, 2020/08/17
- [RFC v4 44/70] target/riscv: rvv-1.0: widening integer multiply-add instructions, frank . chang, 2020/08/17
- [RFC v4 45/70] target/riscv: rvv-1.0: add Zvqmac extension, frank . chang, 2020/08/17