qemu-devel
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH-for-5.2] target/mips: Report unimplemented cache() operations


From: Philippe Mathieu-Daudé
Subject: Re: [PATCH-for-5.2] target/mips: Report unimplemented cache() operations
Date: Thu, 6 Aug 2020 22:11:43 +0200
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0

On 8/6/20 8:01 PM, Jiaxun Yang wrote:
> 在 2020/8/6 下午8:26, Philippe Mathieu-Daudé 写道:
>> We only implement the Index[Store/Load]Tag from the 'cache' opcode.
>> Instead of ignoring the other cache operations, report them as
>> unimplemented.
> 
> Hmm, I don't think we have anything to do with Invalidate/Writeback etc.
> opcodes
> in QEMU. Why do we log this?

I'm noticed this code is run on Linux 3.3.8 (4KEc):

    8880:       3082000f        andi    v0,a0,0xf
    8884:       10800008        beqz    a0,88a8
    8888:       00a21021        addu    v0,a1,v0
    888c:       08002227        j       889c
    8890:       00001821        move    v1,zero
    8894:       bcf90000        cache   0x19,0(a3)
    8898:       24630010        addiu   v1,v1,16
    889c:       0062302b        sltu    a2,v1,v0
    88a0:       14c0fffc        bnez    a2,8894
    88a4:       00833821        addu    a3,a0,v1
    88a8:       03e00008        jr      ra
    88ac:       00000000        nop

Why silently ignore the opcode is not implemented instead of logging it?

> 
> Thanks.
> 
> - Jiaxun
> 
>>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>>   target/mips/op_helper.c | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
>> index 9552b280e0..7f87e57c8e 100644
>> --- a/target/mips/op_helper.c
>> +++ b/target/mips/op_helper.c
>> @@ -1583,6 +1583,8 @@ void helper_cache(CPUMIPSState *env,
>> target_ulong addr, uint32_t op)
>>           /* Index Load Tag */
>>           memory_region_dispatch_read(env->itc_tag, index,
>> &env->CP0_TagLo,
>>                                       MO_64, MEMTXATTRS_UNSPECIFIED);
>> +    } else {
>> +        qemu_log_mask(LOG_UNIMP, "cache %u\n", op);
>>       }
>>   #endif
>>   }
> 



reply via email to

[Prev in Thread] Current Thread [Next in Thread]