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Re: [RFC v2 40/76] target/riscv: rvv-0.9: floating-point move instructio
From: |
Richard Henderson |
Subject: |
Re: [RFC v2 40/76] target/riscv: rvv-0.9: floating-point move instruction |
Date: |
Thu, 30 Jul 2020 13:05:33 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 7/30/20 12:57 PM, Richard Henderson wrote:
> On 7/22/20 2:16 AM, frank.chang@sifive.com wrote:
>> + (s->sew < MO_32)) {
>> + /* SEW < FLEN */
>> + TCGv_i64 t1 = tcg_temp_new_i64();
>> + TCGv_i32 sew = tcg_const_i32(1 << (s->sew + 3));
>> + gen_helper_narrower_nanbox_fpr(t1, cpu_fpr[a->rs1],
>> + sew, cpu_env);
>
> Also, while there is currently one function, gen_nanbox_s, you'll want to add
> gen_nanbox_h to match.
Oops, I forgot which way your helper worked.
The correct function is gen_check_nanbox_s.
r~
- Re: [RFC v2 35/76] target/riscv: rvv-0.9: iota instruction, (continued)
- [RFC v2 36/76] target/riscv: rvv-0.9: element index instruction, frank . chang, 2020/07/22
- [RFC v2 37/76] target/riscv: rvv-0.9: allow load element with sign-extended, frank . chang, 2020/07/22
- [RFC v2 38/76] target/riscv: rvv-0.9: register gather instructions, frank . chang, 2020/07/22
- [RFC v2 39/76] target/riscv: rvv-0.9: integer scalar move instructions, frank . chang, 2020/07/22
- [RFC v2 40/76] target/riscv: rvv-0.9: floating-point move instruction, frank . chang, 2020/07/22
- [RFC v2 41/76] target/riscv: rvv-0.9: floating-point scalar move instructions, frank . chang, 2020/07/22
- [RFC v2 42/76] target/riscv: rvv-0.9: whole register move instructions, frank . chang, 2020/07/22
- [RFC v2 43/76] target/riscv: rvv-0.9: integer extension instructions, frank . chang, 2020/07/22
- [RFC v2 44/76] target/riscv: rvv-0.9: single-width averaging add and subtract instructions, frank . chang, 2020/07/22