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[PULL 4/5] hw/riscv: sifive_e: Correct debug block size
From: |
Alistair Francis |
Subject: |
[PULL 4/5] hw/riscv: sifive_e: Correct debug block size |
Date: |
Wed, 22 Jul 2020 09:48:37 -0700 |
From: Bin Meng <bmeng.cn@gmail.com>
Currently the debug region size is set to 0x100, but according to
FE310-G000 and FE310-G002 manuals:
FE310-G000: 0x100 - 0xFFF
FE310-G002: 0x0 - 0xFFF
Change the size to 0x1000 that applies to both.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1594891856-15474-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_e.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 7bb97b463d..c8b060486a 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -54,7 +54,7 @@ static const struct MemmapEntry {
hwaddr base;
hwaddr size;
} sifive_e_memmap[] = {
- [SIFIVE_E_DEBUG] = { 0x0, 0x100 },
+ [SIFIVE_E_DEBUG] = { 0x0, 0x1000 },
[SIFIVE_E_MROM] = { 0x1000, 0x2000 },
[SIFIVE_E_OTP] = { 0x20000, 0x2000 },
[SIFIVE_E_CLINT] = { 0x2000000, 0x10000 },
--
2.27.0
- [PULL 0/5] riscv-to-apply queue, Alistair Francis, 2020/07/22
- [PULL 1/5] goldfish_rtc: Fix non-atomic read behaviour of TIME_LOW/TIME_HIGH, Alistair Francis, 2020/07/22
- [PULL 2/5] target/riscv: Quiet Coverity complains about vamo*, Alistair Francis, 2020/07/22
- [PULL 4/5] hw/riscv: sifive_e: Correct debug block size,
Alistair Francis <=
- [PULL 3/5] target/riscv: fix vector index load/store constraints, Alistair Francis, 2020/07/22
- [PULL 5/5] target/riscv: Fix the range of pmpcfg of CSR funcion table, Alistair Francis, 2020/07/22
- Re: [PULL 0/5] riscv-to-apply queue, Peter Maydell, 2020/07/24