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[RFC v2 21/76] target/riscv: rvv-0.9: configure instructions
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From: |
frank . chang |
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Subject: |
[RFC v2 21/76] target/riscv: rvv-0.9: configure instructions |
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Date: |
Wed, 22 Jul 2020 17:15:44 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 12 ++++++++----
target/riscv/vector_helper.c | 10 +++++++++-
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 85738ba4f7..ca2ae59bb3 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -98,8 +98,10 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
s2 = tcg_temp_new();
dst = tcg_temp_new();
- /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
- if (a->rs1 == 0) {
+ if (a->rd == 0 && a->rs1 == 0) {
+ s1 = tcg_temp_new();
+ tcg_gen_mov_tl(s1, cpu_vl);
+ } else if (a->rs1 == 0) {
/* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
s1 = tcg_const_tl(RV_VLEN_MAX);
} else {
@@ -131,8 +133,10 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli
*a)
s2 = tcg_const_tl(a->zimm);
dst = tcg_temp_new();
- /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
- if (a->rs1 == 0) {
+ if (a->rd == 0 && a->rs1 == 0) {
+ s1 = tcg_temp_new();
+ tcg_gen_mov_tl(s1, cpu_vl);
+ } else if (a->rs1 == 0) {
/* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
s1 = tcg_const_tl(RV_VLEN_MAX);
} else {
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index fb689ab3f9..9320eeabfd 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -36,7 +36,15 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong
s1,
bool vill = FIELD_EX64(s2, VTYPE, VILL);
target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED);
- if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
+ uint64_t lmul = (FIELD_EX64(s2, VTYPE, VFLMUL) << 2)
+ | FIELD_EX64(s2, VTYPE, VLMUL);
+ float vflmul = flmul_table[lmul];
+
+ if ((sew > cpu->cfg.elen)
+ || vill
+ || vflmul < ((float)sew / cpu->cfg.elen)
+ || (ediv != 0)
+ || (reserved != 0)) {
/* only set vill bit. */
env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
env->vl = 0;
--
2.17.1
- Re: [RFC v2 16/76] target/riscv: rvv-0.9: add VMA and VTA, (continued)
- [RFC v2 20/76] target/riscv: rvv-0.9: apply narrower nanbox helper in opfvf_trans, frank . chang, 2020/07/22
- [RFC v2 21/76] target/riscv: rvv-0.9: configure instructions,
frank . chang <=
- [RFC v2 22/76] target/riscv: rvv-0.9: stride load and store instructions, frank . chang, 2020/07/22
- [RFC v2 23/76] target/riscv: rvv-0.9: index load and store instructions, frank . chang, 2020/07/22
- [RFC v2 24/76] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns, frank . chang, 2020/07/22
- [RFC v2 25/76] target/riscv: rvv-0.9: fault-only-first unit stride load, frank . chang, 2020/07/22
- [RFC v2 26/76] target/riscv: rvv-0.9: amo operations, frank . chang, 2020/07/22
- [RFC v2 27/76] target/riscv: rvv-0.9: load/store whole register instructions, frank . chang, 2020/07/22
- [RFC v2 28/76] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns, frank . chang, 2020/07/22