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[PULL 06/15] RISC-V: Support 64 bit start address
From: |
Alistair Francis |
Subject: |
[PULL 06/15] RISC-V: Support 64 bit start address |
Date: |
Mon, 13 Jul 2020 17:32:45 -0700 |
From: Atish Patra <atish.patra@wdc.com>
Even though the start address in ROM code is declared as a 64 bit address
for RV64, it can't be used as upper bits are set to zero in ROM code.
Update the ROM code correctly to reflect the 64bit value.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20200701183949.398134-5-atish.patra@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/boot.c | 6 +++++-
hw/riscv/sifive_u.c | 6 +++++-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index feff6e3f4e..4c6c101ff1 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -226,7 +226,11 @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr
rom_base,
uint32_t fdt_load_addr, void *fdt)
{
int i;
+ uint32_t start_addr_hi32 = 0x00000000;
+ #if defined(TARGET_RISCV64)
+ start_addr_hi32 = start_addr >> 32;
+ #endif
/* reset vector */
uint32_t reset_vec[10] = {
0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
@@ -241,7 +245,7 @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr
rom_base,
#endif
0x00028067, /* jr t0 */
start_addr, /* start: .dword */
- 0x00000000,
+ start_addr_hi32,
fdt_load_addr, /* fdt_laddr: .dword */
0x00000000,
/* fw_dyn: */
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 46e6ed90ca..6595ab3f87 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -378,6 +378,7 @@ static void sifive_u_machine_init(MachineState *machine)
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *flash0 = g_new(MemoryRegion, 1);
target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
+ uint32_t start_addr_hi32 = 0x00000000;
int i;
uint32_t fdt_load_addr;
uint64_t kernel_entry;
@@ -460,6 +461,9 @@ static void sifive_u_machine_init(MachineState *machine)
/* Compute the fdt load address in dram */
fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base,
machine->ram_size, s->fdt);
+ #if defined(TARGET_RISCV64)
+ start_addr_hi32 = start_addr >> 32;
+ #endif
/* reset vector */
uint32_t reset_vec[11] = {
@@ -476,7 +480,7 @@ static void sifive_u_machine_init(MachineState *machine)
#endif
0x00028067, /* jr t0 */
start_addr, /* start: .dword */
- 0x00000000,
+ start_addr_hi32,
fdt_load_addr, /* fdt_laddr: .dword */
0x00000000,
/* fw_dyn: */
--
2.27.0
- [PULL 00/15] riscv-to-apply queue, Alistair Francis, 2020/07/13
- [PULL 01/15] MAINTAINERS: Add an entry for OpenSBI firmware, Alistair Francis, 2020/07/13
- [PULL 02/15] hw/riscv: virt: Sort the SoC memmap table entries, Alistair Francis, 2020/07/13
- [PULL 04/15] RISC-V: Copy the fdt in dram instead of ROM, Alistair Francis, 2020/07/13
- [PULL 03/15] riscv: Unify Qemu's reset vector code path, Alistair Francis, 2020/07/13
- [PULL 05/15] riscv: Add opensbi firmware dynamic support, Alistair Francis, 2020/07/13
- [PULL 06/15] RISC-V: Support 64 bit start address,
Alistair Francis <=
- [PULL 07/15] hw/riscv: Modify MROM size to end at 0x10000, Alistair Francis, 2020/07/13
- [PULL 08/15] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion, Alistair Francis, 2020/07/13
- [PULL 09/15] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64(), Alistair Francis, 2020/07/13
- [PULL 10/15] target/riscv: fix return value of do_opivx_widen(), Alistair Francis, 2020/07/13
- [PULL 11/15] target/riscv: fix vill bit index in vtype register, Alistair Francis, 2020/07/13
- [PULL 12/15] hw/char: Convert the Ibex UART to use the qdev Clock model, Alistair Francis, 2020/07/13
- [PULL 13/15] hw/char: Convert the Ibex UART to use the registerfields API, Alistair Francis, 2020/07/13
- [PULL 14/15] tcg/riscv: Remove superfluous breaks, Alistair Francis, 2020/07/13
- [PULL 15/15] target/riscv: Fix pmp NA4 implementation, Alistair Francis, 2020/07/13
- Re: [PULL 00/15] riscv-to-apply queue, Alistair Francis, 2020/07/13