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[PATCH v4 09/22] target/xtensa: add DFPU option
From: |
Max Filippov |
Subject: |
[PATCH v4 09/22] target/xtensa: add DFPU option |
Date: |
Sat, 11 Jul 2020 04:06:44 -0700 |
Double precision floating point unit is a FPU implementation different
from the FPU2000 in the following ways:
- it may be configured with only single or with both single and double
precision operations support;
- it may be configured with division and square root opcodes;
- FSR register accumulates inValid, division by Zero, Overflow,
Underflow and Inexact result flags of operations;
- QNaNs and SNaNs are handled properly;
- NaN propagation rules are different.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
Changes v3->v4:
- new patch split from the next one
target/xtensa/cpu.h | 2 ++
target/xtensa/overlay_tool.h | 23 +++++++++++++++++++++++
2 files changed, 25 insertions(+)
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 960f6573447f..6fc1565000b6 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -52,6 +52,8 @@ enum {
XTENSA_OPTION_COPROCESSOR,
XTENSA_OPTION_BOOLEAN,
XTENSA_OPTION_FP_COPROCESSOR,
+ XTENSA_OPTION_DFP_COPROCESSOR,
+ XTENSA_OPTION_DFPU_SINGLE_ONLY,
XTENSA_OPTION_MP_SYNCHRO,
XTENSA_OPTION_CONDITIONAL_STORE,
XTENSA_OPTION_ATOMCTL,
diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h
index eb9f08af0bf6..9f0846c86b65 100644
--- a/target/xtensa/overlay_tool.h
+++ b/target/xtensa/overlay_tool.h
@@ -39,6 +39,26 @@
#define XCHAL_HAVE_DEPBITS 0
#endif
+#ifndef XCHAL_HAVE_DFP
+#define XCHAL_HAVE_DFP 0
+#endif
+
+#ifndef XCHAL_HAVE_DFPU_SINGLE_ONLY
+#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0
+#endif
+
+#ifndef XCHAL_HAVE_DFPU_SINGLE_DOUBLE
+#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE XCHAL_HAVE_DFP
+#endif
+
+/*
+ * We need to know the type of FP unit, not only its precision.
+ * Unfortunately XCHAL macros don't tell this explicitly.
+ */
+#define XCHAL_HAVE_DFPU (XCHAL_HAVE_DFP || \
+ XCHAL_HAVE_DFPU_SINGLE_ONLY || \
+ XCHAL_HAVE_DFPU_SINGLE_DOUBLE)
+
#ifndef XCHAL_HAVE_DIV32
#define XCHAL_HAVE_DIV32 0
#endif
@@ -99,6 +119,9 @@
XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \
XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \
XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
+ XCHAL_OPTION(XCHAL_HAVE_DFPU, XTENSA_OPTION_DFP_COPROCESSOR) | \
+ XCHAL_OPTION(XCHAL_HAVE_DFPU_SINGLE_ONLY, \
+ XTENSA_OPTION_DFPU_SINGLE_ONLY) | \
XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
XCHAL_OPTION(((XCHAL_HAVE_S32C1I && XCHAL_HW_VERSION >= 230000) || \
--
2.20.1
- [PATCH v4 00/22] target/xtensa: implement double precision FPU, Max Filippov, 2020/07/11
- [PATCH v4 01/22] softfloat: make NO_SIGNALING_NANS runtime property, Max Filippov, 2020/07/11
- [PATCH v4 02/22] softfloat: pass float_status pointer to pickNaN, Max Filippov, 2020/07/11
- [PATCH v4 03/22] softfloat: add xtensa specialization for pickNaNMulAdd, Max Filippov, 2020/07/11
- [PATCH v4 04/22] target/xtensa: add geometry to xtensa_get_regfile_by_name, Max Filippov, 2020/07/11
- [PATCH v4 05/22] target/xtensa: support copying registers up to 64 bits wide, Max Filippov, 2020/07/11
- [PATCH v4 06/22] target/xtensa: rename FPU2000 translators and helpers, Max Filippov, 2020/07/11
- [PATCH v4 07/22] target/xtensa: move FSR/FCR register accessors, Max Filippov, 2020/07/11
- [PATCH v4 08/22] target/xtensa: don't access BR regfile directly, Max Filippov, 2020/07/11
- [PATCH v4 09/22] target/xtensa: add DFPU option,
Max Filippov <=
- [PATCH v4 11/22] target/xtensa: implement FPU division and square root, Max Filippov, 2020/07/11
- [PATCH v4 12/22] tests/tcg/xtensa: fix test execution on ISS, Max Filippov, 2020/07/11
- [PATCH v4 13/22] tests/tcg/xtensa: update test_fp0_arith for DFPU, Max Filippov, 2020/07/11
- [PATCH v4 14/22] tests/tcg/xtensa: expand madd tests, Max Filippov, 2020/07/11
- [PATCH v4 16/22] tests/tcg/xtensa: update test_fp1 for DFPU, Max Filippov, 2020/07/11
- [PATCH v4 10/22] target/xtensa: add DFPU registers and opcodes, Max Filippov, 2020/07/11
- [PATCH v4 15/22] tests/tcg/xtensa: update test_fp0_conv for DFPU, Max Filippov, 2020/07/11
- [PATCH v4 18/22] tests/tcg/xtensa: add fp0 div and sqrt tests, Max Filippov, 2020/07/11
- [PATCH v4 19/22] tests/tcg/xtensa: test double precision load/store, Max Filippov, 2020/07/11
- [PATCH v4 20/22] tests/tcg/xtensa: add DFP0 arithmetic tests, Max Filippov, 2020/07/11