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Re: [RFC 14/65] target/riscv: rvv-0.9: stride load and store instruction
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From: |
Richard Henderson |
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Subject: |
Re: [RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions |
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Date: |
Fri, 10 Jul 2020 11:15:30 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 |
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> # *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
> -vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm
> -vlh_v ... 100 . 00000 ..... 101 ..... 0000111 @r2_nfvm
> -vlw_v ... 100 . 00000 ..... 110 ..... 0000111 @r2_nfvm
Again, something you can't do until 0.7.1 is not supported.
If you don't want to simultaneously support 0.7.1 and 0.9/1.0, then you should
simply remove 0.7.1 in the first patch, so that there's no confusion.
Is the rest of it mostly renaming? You should definitely expand on what you're
doing within each patch description. A description of what has changed in the
spec since 0.7.1 will help the reviewer validate that you've gotten all of the
corner cases.
I am going to stop reviewing this patch series now, as I expect that most of
the remaining patches will have similar comments.
r~
- [RFC 41/65] target/riscv: rvv-0.9: floating-point compare instructions, (continued)
- [RFC 41/65] target/riscv: rvv-0.9: floating-point compare instructions, frank . chang, 2020/07/10
- [RFC 43/65] target/riscv: rvv-0.9: widening integer reduction instructions, frank . chang, 2020/07/10
- [RFC 49/65] target/riscv: rvv-0.9: floating-point move instructions, frank . chang, 2020/07/10
- [RFC 51/65] target/riscv: rvv-0.9: single-width floating-point reduction, frank . chang, 2020/07/10
- [RFC 62/65] fpu: add api to handle alternative sNaN propagation, frank . chang, 2020/07/10
- [RFC 64/65] target/riscv: use softfloat lib float16 comparison functions, frank . chang, 2020/07/10
- [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, frank . chang, 2020/07/10
- [RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions, frank . chang, 2020/07/10
- Re: [RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions,
Richard Henderson <=
- [RFC 19/65] target/riscv: rvv-0.9: load/store whole register instructions, frank . chang, 2020/07/10
- [RFC 20/65] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns, frank . chang, 2020/07/10
- [RFC 30/65] target/riscv: rvv-0.9: floating-point scalar move instructions, frank . chang, 2020/07/10
- [RFC 32/65] target/riscv: rvv-0.9: integer extension instructions, frank . chang, 2020/07/10
- [RFC 34/65] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow, frank . chang, 2020/07/10
- [RFC 37/65] target/riscv: rvv-0.9: quad-widening integer multiply-add instructions, frank . chang, 2020/07/10
- [RFC 46/65] target/riscv: rvv-0.9: slide instructions, frank . chang, 2020/07/10
- [RFC 47/65] target/riscv: rvv-0.9: floating-point slide instructions, frank . chang, 2020/07/10
- [RFC 52/65] target/riscv: rvv-0.9: widening floating-point reduction instructions, frank . chang, 2020/07/10