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[PATCH v3 16/21] tests/tcg/xtensa: update test_lsc for DFPU
From: |
Max Filippov |
Subject: |
[PATCH v3 16/21] tests/tcg/xtensa: update test_lsc for DFPU |
Date: |
Wed, 8 Jul 2020 15:20:56 -0700 |
DFPU doesn't have pre-increment FP load/store opcodes, it has
post-increment opcodes instead. Test increment opcodes present in the
current config.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
tests/tcg/xtensa/test_lsc.S | 47 +++++++++++++++++++++++++++----------
1 file changed, 34 insertions(+), 13 deletions(-)
diff --git a/tests/tcg/xtensa/test_lsc.S b/tests/tcg/xtensa/test_lsc.S
index 0578bf19e72e..9d59c1815a9e 100644
--- a/tests/tcg/xtensa/test_lsc.S
+++ b/tests/tcg/xtensa/test_lsc.S
@@ -1,4 +1,5 @@
#include "macros.inc"
+#include "fpu.h"
test_suite lsc
@@ -9,9 +10,14 @@ test lsi
wsr a2, cpenable
movi a2, 1f
- lsi f0, a2, 0
lsi f1, a2, 4
+#if DFPU
+ lsi f2, a2, 8
+ lsip f0, a2, 8
+#else
+ lsi f0, a2, 0
lsiu f2, a2, 8
+#endif
movi a3, 1f + 8
assert eq, a2, a3
rfr a2, f0
@@ -34,13 +40,18 @@ test ssi
movi a2, 1f
movi a3, 0x40800000
wfr f3, a3
- ssi f3, a2, 0
movi a3, 0x40a00000
wfr f4, a3
- ssi f4, a2, 4
movi a3, 0x40c00000
wfr f5, a3
+ ssi f4, a2, 4
+#if DFPU
+ ssi f5, a2, 8
+ ssip f3, a2, 8
+#else
+ ssi f3, a2, 0
ssiu f5, a2, 8
+#endif
movi a3, 1f + 8
assert eq, a2, a3
l32i a4, a2, -8
@@ -62,11 +73,16 @@ test_end
test lsx
movi a2, 1f
movi a3, 0
+ movi a4, 4
+ movi a5, 8
+ lsx f7, a2, a4
+#if DFPU
+ lsx f8, a2, a5
+ lsxp f6, a2, a5
+#else
lsx f6, a2, a3
- movi a3, 4
- lsx f7, a2, a3
- movi a3, 8
- lsxu f8, a2, a3
+ lsxu f8, a2, a5
+#endif
movi a3, 1f + 8
assert eq, a2, a3
rfr a2, f6
@@ -87,18 +103,23 @@ test_end
test ssx
movi a2, 1f
- movi a3, 0
movi a4, 0x41200000
wfr f9, a4
- ssx f9, a2, a3
- movi a3, 4
movi a4, 0x41300000
wfr f10, a4
- ssx f10, a2, a3
- movi a3, 8
movi a4, 0x41400000
wfr f11, a4
- ssxu f11, a2, a3
+ movi a3, 0
+ movi a4, 4
+ movi a5, 8
+ ssx f10, a2, a4
+#if DFPU
+ ssx f11, a2, a5
+ ssxp f9, a2, a5
+#else
+ ssx f9, a2, a3
+ ssxu f11, a2, a5
+#endif
movi a3, 1f + 8
assert eq, a2, a3
l32i a4, a2, -8
--
2.20.1
- [PATCH v3 06/21] target/xtensa: rename FPU2000 translators and helpers, (continued)
- [PATCH v3 06/21] target/xtensa: rename FPU2000 translators and helpers, Max Filippov, 2020/07/08
- [PATCH v3 07/21] target/xtensa: move FSR/FCR register accessors, Max Filippov, 2020/07/08
- [PATCH v3 08/21] target/xtensa: don't access BR regfile directly, Max Filippov, 2020/07/08
- [PATCH v3 10/21] target/xtensa: implement FPU division and square root, Max Filippov, 2020/07/08
- [PATCH v3 11/21] tests/tcg/xtensa: fix test execution on ISS, Max Filippov, 2020/07/08
- [PATCH v3 13/21] tests/tcg/xtensa: expand madd tests, Max Filippov, 2020/07/08
- [PATCH v3 12/21] tests/tcg/xtensa: update test_fp0_arith for DFPU, Max Filippov, 2020/07/08
- [PATCH v3 09/21] target/xtensa: add DFP option, registers and opcodes, Max Filippov, 2020/07/08
- [PATCH v3 14/21] tests/tcg/xtensa: update test_fp0_conv for DFPU, Max Filippov, 2020/07/08
- [PATCH v3 18/21] tests/tcg/xtensa: test double precision load/store, Max Filippov, 2020/07/08
- [PATCH v3 16/21] tests/tcg/xtensa: update test_lsc for DFPU,
Max Filippov <=
- [PATCH v3 17/21] tests/tcg/xtensa: add fp0 div and sqrt tests, Max Filippov, 2020/07/08
- [PATCH v3 15/21] tests/tcg/xtensa: update test_fp1 for DFPU, Max Filippov, 2020/07/08
- [PATCH v3 20/21] target/xtensa: import de233_fpu core, Max Filippov, 2020/07/08
- [PATCH v3 19/21] tests/tcg/xtensa: add DFP0 arithmetic tests, Max Filippov, 2020/07/08