Re: [PULL v2 12/64] target/riscv: add vector amo operations

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Re: [PULL v2 12/64] target/riscv: add vector amo operations

From:	Richard Henderson
Subject:	Re: [PULL v2 12/64] target/riscv: add vector amo operations
Date:	Tue, 7 Jul 2020 07:33:55 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0

On 7/7/20 7:26 AM, LIU Zhiwei wrote:
> As  there are not only the atomic instructions have this question, all
> instructions that use
> GEN_VEXT_TRANS have the same question too. It's some difficult to address this
> question by this way.

Oh yes, I missed that.  Ok, perhaps the simpler assert would be best right now
before softfreeze.


r~

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[PULL v2 05/64] target/riscv: implementation-defined constant parameters, (continued)
- [PULL v2 05/64] target/riscv: implementation-defined constant parameters, Alistair Francis, 2020/07/02
- [PULL v2 06/64] target/riscv: support vector extension csr, Alistair Francis, 2020/07/02
- [PULL v2 14/64] target/riscv: vector widening integer add and subtract, Alistair Francis, 2020/07/02
- [PULL v2 10/64] target/riscv: add vector index load and store instructions, Alistair Francis, 2020/07/02
- [PULL v2 22/64] target/riscv: vector integer divide instructions, Alistair Francis, 2020/07/02
- [PULL v2 04/64] target/riscv: add vector extension field in CPURISCVState, Alistair Francis, 2020/07/02
- [PULL v2 12/64] target/riscv: add vector amo operations, Alistair Francis, 2020/07/02
  - Re: [PULL v2 12/64] target/riscv: add vector amo operations, Peter Maydell, 2020/07/05
    - Re: [PULL v2 12/64] target/riscv: add vector amo operations, Richard Henderson, 2020/07/06
    - Re: [PULL v2 12/64] target/riscv: add vector amo operations, LIU Zhiwei, 2020/07/07
    - Re: [PULL v2 12/64] target/riscv: add vector amo operations, Richard Henderson <=
    - Re: [PULL v2 12/64] target/riscv: add vector amo operations, Alistair Francis, 2020/07/06
    - Re: [PULL v2 12/64] target/riscv: add vector amo operations, LIU Zhiwei, 2020/07/06
- [PULL v2 09/64] target/riscv: add vector stride load and store instructions, Alistair Francis, 2020/07/02
- [PULL v2 17/64] target/riscv: vector single-width bit shift instructions, Alistair Francis, 2020/07/02
- [PULL v2 13/64] target/riscv: vector single-width integer add and subtract, Alistair Francis, 2020/07/02
- [PULL v2 15/64] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions, Alistair Francis, 2020/07/02
- [PULL v2 19/64] target/riscv: vector integer comparison instructions, Alistair Francis, 2020/07/02
- [PULL v2 18/64] target/riscv: vector narrowing integer right shift instructions, Alistair Francis, 2020/07/02
- [PULL v2 11/64] target/riscv: add fault-only-first unit stride load, Alistair Francis, 2020/07/02
- [PULL v2 20/64] target/riscv: vector integer min/max instructions, Alistair Francis, 2020/07/02

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