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Re: [PATCH 01/21] softfloat: make NO_SIGNALING_NANS runtime property
From: |
Alex Bennée |
Subject: |
Re: [PATCH 01/21] softfloat: make NO_SIGNALING_NANS runtime property |
Date: |
Tue, 07 Jul 2020 11:28:13 +0100 |
User-agent: |
mu4e 1.5.4; emacs 28.0.50 |
Max Filippov <jcmvbkbc@gmail.com> writes:
> target/xtensa, the only user of NO_SIGNALING_NANS macro has FPU
> implementations with and without the corresponding property. With
> NO_SIGNALING_NANS being a macro they cannot be a part of the same QEMU
> executable.
> Replace macro with new property in float_status to allow cores with
> different FPU implementations coexist.
>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Cc: "Alex Bennée" <alex.bennee@linaro.org>
> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
> ---
> fpu/softfloat-specialize.inc.c | 228 ++++++++++++++++----------------
> include/fpu/softfloat-helpers.h | 5 +
> include/fpu/softfloat-types.h | 1 +
> 3 files changed, 117 insertions(+), 117 deletions(-)
>
> diff --git a/fpu/softfloat-specialize.inc.c b/fpu/softfloat-specialize.inc.c
> index 44f5b661f831..b26bc039b0b6 100644
> --- a/fpu/softfloat-specialize.inc.c
> +++ b/fpu/softfloat-specialize.inc.c
> @@ -79,13 +79,6 @@ this code that are retained.
> * version 2 or later. See the COPYING file in the top-level directory.
> */
>
> -/* Define for architectures which deviate from IEEE in not supporting
> - * signaling NaNs (so all NaNs are treated as quiet).
> - */
> -#if defined(TARGET_XTENSA)
> -#define NO_SIGNALING_NANS 1
> -#endif
> -
> /* Define how the architecture discriminates signaling NaNs.
> * This done with the most significant bit of the fraction.
> * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008
> @@ -111,12 +104,12 @@ static inline bool snan_bit_is_one(float_status *status)
>
> static bool parts_is_snan_frac(uint64_t frac, float_status *status)
> {
> -#ifdef NO_SIGNALING_NANS
> - return false;
> -#else
> - bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1);
> - return msb == snan_bit_is_one(status);
> -#endif
> + if (status->no_signaling_nans) {
> + return false;
I have no objection in principle but seeing as we go to the trouble of
allowing snan_bit_is_one() to constant fold away I think it would be
worth doing the same with a no_signalling_nans(status). We can then
avoid an admittedly well predicted test for the non XTENSA case.
> + } else {
> + bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1);
> + return msb == snan_bit_is_one(status);
> + }
> }
>
>
> /*----------------------------------------------------------------------------
> @@ -170,9 +163,10 @@ static FloatParts parts_default_nan(float_status *status)
>
> static FloatParts parts_silence_nan(FloatParts a, float_status *status)
> {
> -#ifdef NO_SIGNALING_NANS
> - g_assert_not_reached();
We could then keep the assert:
g_assert(!no_signaling_nan(status))
<snip>
> return status->tininess_before_rounding;
> diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
> index 7680193ebc1c..10bd208e559f 100644
> --- a/include/fpu/softfloat-types.h
> +++ b/include/fpu/softfloat-types.h
> @@ -167,6 +167,7 @@ typedef struct float_status {
> bool default_nan_mode;
> /* not always used -- see snan_bit_is_one() in
> softfloat-specialize.h */
and then expand this comment:
/* the flags bellow are not used on all specializations and may
* constant fold away (see snan_bit_is_one()/no_signalling_nans() in
* softfloat-specialize.h)
*/
> bool snan_bit_is_one;
> + bool no_signaling_nans;
> } float_status;
>
> #endif /* SOFTFLOAT_TYPES_H */
--
Alex Bennée
- [PATCH 00/21] target/xtensa: implement double precision FPU, Max Filippov, 2020/07/06
- [PATCH 02/21] softfloat: pass float_status pointer to pickNaN, Max Filippov, 2020/07/06
- [PATCH 01/21] softfloat: make NO_SIGNALING_NANS runtime property, Max Filippov, 2020/07/06
- [PATCH 03/21] softfloat: add xtensa specialization for pickNaNMulAdd, Max Filippov, 2020/07/06
- [PATCH 04/21] target/xtensa: add geometry to xtensa_get_regfile_by_name, Max Filippov, 2020/07/06
- [PATCH 06/21] target/xtensa: rename FPU2000 translators and helpers, Max Filippov, 2020/07/06
- [PATCH 07/21] target/xtensa: move FSR/FCR register accessors, Max Filippov, 2020/07/06