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[RFC PATCH 3/3] target/avr: Fix SBRC/SBRS instructions
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From: |
Philippe Mathieu-Daudé |
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Subject: |
[RFC PATCH 3/3] target/avr: Fix SBRC/SBRS instructions |
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Date: |
Tue, 7 Jul 2020 08:46:46 +0200 |
SBRC/SBRS instructions seem to be inverted.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/avr/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index fe03e676df..2f77fe3ba7 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -1385,7 +1385,7 @@ static bool trans_SBRC(DisasContext *ctx, arg_SBRC *a)
{
TCGv Rr = cpu_r[a->rr];
- ctx->skip_cond = TCG_COND_EQ;
+ ctx->skip_cond = TCG_COND_NE;
ctx->skip_var0 = tcg_temp_new();
ctx->free_skip_var0 = true;
@@ -1401,7 +1401,7 @@ static bool trans_SBRS(DisasContext *ctx, arg_SBRS *a)
{
TCGv Rr = cpu_r[a->rr];
- ctx->skip_cond = TCG_COND_NE;
+ ctx->skip_cond = TCG_COND_EQ;
ctx->skip_var0 = tcg_temp_new();
ctx->free_skip_var0 = true;
--
2.21.3