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[PULL 09/34] target/arm: kvm: Handle DABT with no valid ISS
From: |
Peter Maydell |
Subject: |
[PULL 09/34] target/arm: kvm: Handle DABT with no valid ISS |
Date: |
Fri, 3 Jul 2020 17:53:40 +0100 |
From: Beata Michalska <beata.michalska@linaro.org>
On ARMv7 & ARMv8 some load/store instructions might trigger a data abort
exception with no valid ISS info to be decoded. The lack of decode info
makes it at least tricky to emulate those instruction which is one of the
(many) reasons why KVM will not even try to do so.
Add support for handling those by requesting KVM to inject external
dabt into the quest.
Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id: 20200629114110.30723-2-beata.michalska@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/kvm.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 7c672c78b88..3a46f54f1fd 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -39,6 +39,7 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
static bool cap_has_mp_state;
static bool cap_has_inject_serror_esr;
+static bool cap_has_inject_ext_dabt;
static ARMHostCPUFeatures arm_host_cpu_features;
@@ -245,6 +246,16 @@ int kvm_arch_init(MachineState *ms, KVMState *s)
ret = -EINVAL;
}
+ if (kvm_check_extension(s, KVM_CAP_ARM_NISV_TO_USER)) {
+ if (kvm_vm_enable_cap(s, KVM_CAP_ARM_NISV_TO_USER, 0)) {
+ error_report("Failed to enable KVM_CAP_ARM_NISV_TO_USER cap");
+ } else {
+ /* Set status for supporting the external dabt injection */
+ cap_has_inject_ext_dabt = kvm_check_extension(s,
+ KVM_CAP_ARM_INJECT_EXT_DABT);
+ }
+ }
+
return ret;
}
@@ -810,6 +821,42 @@ void kvm_arm_vm_state_change(void *opaque, int running,
RunState state)
}
}
+/**
+ * kvm_arm_handle_dabt_nisv:
+ * @cs: CPUState
+ * @esr_iss: ISS encoding (limited) for the exception from Data Abort
+ * ISV bit set to '0b0' -> no valid instruction syndrome
+ * @fault_ipa: faulting address for the synchronous data abort
+ *
+ * Returns: 0 if the exception has been handled, < 0 otherwise
+ */
+static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss,
+ uint64_t fault_ipa)
+{
+ /*
+ * Request KVM to inject the external data abort into the guest
+ */
+ if (cap_has_inject_ext_dabt) {
+ struct kvm_vcpu_events events = { };
+ /*
+ * The external data abort event will be handled immediately by KVM
+ * using the address fault that triggered the exit on given VCPU.
+ * Requesting injection of the external data abort does not rely
+ * on any other VCPU state. Therefore, in this particular case, the
VCPU
+ * synchronization can be exceptionally skipped.
+ */
+ events.exception.ext_dabt_pending = 1;
+ /* KVM_CAP_ARM_INJECT_EXT_DABT implies KVM_CAP_VCPU_EVENTS */
+ return kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events);
+ } else {
+ error_report("Data abort exception triggered by guest memory access "
+ "at physical address: 0x" TARGET_FMT_lx,
+ (target_ulong)fault_ipa);
+ error_printf("KVM unable to emulate faulting instruction.\n");
+ }
+ return -1;
+}
+
int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
{
int ret = 0;
@@ -820,6 +867,11 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
ret = EXCP_DEBUG;
} /* otherwise return to guest */
break;
+ case KVM_EXIT_ARM_NISV:
+ /* External DABT with no valid iss to decode */
+ ret = kvm_arm_handle_dabt_nisv(cs, run->arm_nisv.esr_iss,
+ run->arm_nisv.fault_ipa);
+ break;
default:
qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
__func__, run->exit_reason);
--
2.20.1
- [PULL 01/34] Add a phy-num property to the i.MX FEC emulator, (continued)
- [PULL 01/34] Add a phy-num property to the i.MX FEC emulator, Peter Maydell, 2020/07/03
- [PULL 03/34] Select MDIO device 2 and 1 as PHY devices for i.MX6UL EVK board., Peter Maydell, 2020/07/03
- [PULL 02/34] Add the ability to select a different PHY for each i.MX6UL FEC interface, Peter Maydell, 2020/07/03
- [PULL 04/34] qdev: Introduce DEFINE_PROP_RESERVED_REGION, Peter Maydell, 2020/07/03
- [PULL 05/34] virtio-iommu: Implement RESV_MEM probe request, Peter Maydell, 2020/07/03
- [PULL 06/34] virtio-iommu: Handle reserved regions in the translation process, Peter Maydell, 2020/07/03
- [PULL 08/34] hw/arm/virt: Let the virtio-iommu bypass MSIs, Peter Maydell, 2020/07/03
- [PULL 07/34] virtio-iommu-pci: Add array of Interval properties, Peter Maydell, 2020/07/03
- [PULL 09/34] target/arm: kvm: Handle DABT with no valid ISS,
Peter Maydell <=
- [PULL 10/34] target/arm: kvm: Handle misconfigured dabt injection, Peter Maydell, 2020/07/03
- [PULL 12/34] tests/acpi: virt: allow DSDT acpi table changes, Peter Maydell, 2020/07/03
- [PULL 13/34] hw/arm/virt-acpi-build: Only expose flash on older machine types, Peter Maydell, 2020/07/03
- [PULL 11/34] tests/acpi: remove stale allowed tables, Peter Maydell, 2020/07/03
- [PULL 14/34] tests/acpi: virt: update golden masters for DSDT, Peter Maydell, 2020/07/03
- [PULL 15/34] target/arm: Fix temp double-free in sve ldr/str, Peter Maydell, 2020/07/03
- [PULL 16/34] hw/display/bcm2835_fb.c: Initialize all fields of struct, Peter Maydell, 2020/07/03
- [PULL 17/34] hw/arm/spitz: Detabify, Peter Maydell, 2020/07/03
- [PULL 19/34] hw/arm/spitz: Keep pointers to MPU and SSI devices in SpitzMachineState, Peter Maydell, 2020/07/03
- [PULL 18/34] hw/arm/spitz: Create SpitzMachineClass abstract base class, Peter Maydell, 2020/07/03