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Re: [PULL 02/63] riscv: plic: Add a couple of mising sifive_plic_update
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From: |
Jessica Clarke |
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Subject: |
Re: [PULL 02/63] riscv: plic: Add a couple of mising sifive_plic_update calls |
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Date: |
Fri, 26 Jun 2020 23:01:20 +0100 |
On 26 Jun 2020, at 22:43, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> From: Jessica Clarke <jrtc27@jrtc27.com>
>
> Claiming an interrupt and changing the source priority both potentially
> affect whether an interrupt is pending, thus we must re-compute xEIP.
> Note that we don't put the sifive_plic_update inside sifive_plic_claim
> so that the logging of a claim (and the resulting IRQ) happens before
> the state update, making the causal effect clear, and that we drop the
> explicit call to sifive_plic_print_state when claiming since
> sifive_plic_update already does that automatically at the end for us.
>
> This can result in both spurious interrupt storms if you fail to
> complete an IRQ before enabling interrupts (and no other actions occur
> that result in a call to sifive_plic_update), but also more importantly
> lost interrupts if a disabled interrupt is pending and then becomes
> enabled.
>
> Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Message-id: 20200618210649.22451-1-jrtc27@jrtc27.com
> Message-Id: <20200618210649.22451-1-jrtc27@jrtc27.com>
Something went a bit weird here.
Jess
- [PULL 00/63] riscv-to-apply queue, Alistair Francis, 2020/06/26
- [PULL 11/63] target/riscv: add vector amo operations, Alistair Francis, 2020/06/26
- [PULL 12/63] target/riscv: vector single-width integer add and subtract, Alistair Francis, 2020/06/26
- [PULL 13/63] target/riscv: vector widening integer add and subtract, Alistair Francis, 2020/06/26
- [PULL 01/63] riscv: plic: Honour source priorities, Alistair Francis, 2020/06/26
- [PULL 02/63] riscv: plic: Add a couple of mising sifive_plic_update calls, Alistair Francis, 2020/06/26
- Re: [PULL 02/63] riscv: plic: Add a couple of mising sifive_plic_update calls,
Jessica Clarke <=
- [PULL 04/63] target/riscv: implementation-defined constant parameters, Alistair Francis, 2020/06/26
- [PULL 15/63] target/riscv: vector bitwise logical instructions, Alistair Francis, 2020/06/26
- [PULL 05/63] target/riscv: support vector extension csr, Alistair Francis, 2020/06/26
- [PULL 16/63] target/riscv: vector single-width bit shift instructions, Alistair Francis, 2020/06/26
- [PULL 14/63] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions, Alistair Francis, 2020/06/26
- [PULL 03/63] target/riscv: add vector extension field in CPURISCVState, Alistair Francis, 2020/06/26
- [PULL 19/63] target/riscv: vector integer min/max instructions, Alistair Francis, 2020/06/26
- [PULL 35/63] target/riscv: vector widening floating-point multiply, Alistair Francis, 2020/06/26
- [PULL 06/63] target/riscv: add vector configure instruction, Alistair Francis, 2020/06/26