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[PULL 42/57] target/arm: Use mte_check1 for sve LD1R
From: |
Peter Maydell |
Subject: |
[PULL 42/57] target/arm: Use mte_check1 for sve LD1R |
Date: |
Fri, 26 Jun 2020 16:14:09 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-31-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-sve.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 4a613ca6892..4fa521989de 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -4892,7 +4892,7 @@ static bool trans_LD1R_zpri(DisasContext *s,
arg_rpri_load *a)
unsigned esz = dtype_esz[a->dtype];
unsigned msz = dtype_msz(a->dtype);
TCGLabel *over = gen_new_label();
- TCGv_i64 temp;
+ TCGv_i64 temp, clean_addr;
/* If the guarding predicate has no bits set, no load occurs. */
if (psz <= 8) {
@@ -4915,7 +4915,9 @@ static bool trans_LD1R_zpri(DisasContext *s,
arg_rpri_load *a)
/* Load the data. */
temp = tcg_temp_new_i64();
tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << msz);
- tcg_gen_qemu_ld_i64(temp, temp, get_mem_index(s),
+ clean_addr = gen_mte_check1(s, temp, false, true, msz);
+
+ tcg_gen_qemu_ld_i64(temp, clean_addr, get_mem_index(s),
s->be_data | dtype_mop[a->dtype]);
/* Broadcast to *all* elements. */
--
2.20.1
- [PULL 31/57] target/arm: Implement the LDGM, STGM, STZGM instructions, (continued)
- [PULL 31/57] target/arm: Implement the LDGM, STGM, STZGM instructions, Peter Maydell, 2020/06/26
- [PULL 32/57] target/arm: Implement the access tag cache flushes, Peter Maydell, 2020/06/26
- [PULL 33/57] target/arm: Move regime_el to internals.h, Peter Maydell, 2020/06/26
- [PULL 34/57] target/arm: Move regime_tcr to internals.h, Peter Maydell, 2020/06/26
- [PULL 35/57] target/arm: Add gen_mte_check1, Peter Maydell, 2020/06/26
- [PULL 37/57] target/arm: Implement helper_mte_check1, Peter Maydell, 2020/06/26
- [PULL 36/57] target/arm: Add gen_mte_checkN, Peter Maydell, 2020/06/26
- [PULL 41/57] target/arm: Use mte_checkN for sve unpredicated stores, Peter Maydell, 2020/06/26
- [PULL 38/57] target/arm: Implement helper_mte_checkN, Peter Maydell, 2020/06/26
- [PULL 40/57] target/arm: Use mte_checkN for sve unpredicated loads, Peter Maydell, 2020/06/26
- [PULL 42/57] target/arm: Use mte_check1 for sve LD1R,
Peter Maydell <=
- [PULL 43/57] target/arm: Tidy trans_LD1R_zpri, Peter Maydell, 2020/06/26
- [PULL 44/57] target/arm: Add arm_tlb_bti_gp, Peter Maydell, 2020/06/26
- [PULL 48/57] target/arm: Handle TBI for sve scalar + int memory ops, Peter Maydell, 2020/06/26
- [PULL 39/57] target/arm: Add helper_mte_check_zva, Peter Maydell, 2020/06/26
- [PULL 45/57] target/arm: Add mte helpers for sve scalar + int loads, Peter Maydell, 2020/06/26
- [PULL 51/57] target/arm: Implement data cache set allocation tags, Peter Maydell, 2020/06/26
- [PULL 50/57] target/arm: Complete TBI clearing for user-only for SVE, Peter Maydell, 2020/06/26
- [PULL 46/57] target/arm: Add mte helpers for sve scalar + int stores, Peter Maydell, 2020/06/26
- [PULL 47/57] target/arm: Add mte helpers for sve scalar + int ff/nf loads, Peter Maydell, 2020/06/26
- [PULL 52/57] target/arm: Set PSTATE.TCO on exception entry, Peter Maydell, 2020/06/26