[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v9 12/46] target/arm: Implement the GMI instruction
From: |
Richard Henderson |
Subject: |
[PATCH v9 12/46] target/arm: Implement the GMI instruction |
Date: |
Thu, 25 Jun 2020 20:31:10 -0700 |
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v6: Inline the operation.
---
target/arm/translate-a64.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2ec02c8a5f..ee9dfa8e43 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5346,6 +5346,21 @@ static void disas_data_proc_2src(DisasContext *s,
uint32_t insn)
cpu_reg_sp(s, rn));
}
break;
+ case 5: /* GMI */
+ if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) {
+ goto do_unallocated;
+ } else {
+ TCGv_i64 t1 = tcg_const_i64(1);
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ tcg_gen_extract_i64(t2, cpu_reg_sp(s, rn), 56, 4);
+ tcg_gen_shl_i64(t1, t1, t2);
+ tcg_gen_or_i64(cpu_reg(s, rd), cpu_reg(s, rm), t1);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+ }
+ break;
case 8: /* LSLV */
handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd);
break;
--
2.25.1
- [PATCH v9 02/46] target/arm: Improve masking of SCR RES0 bits, (continued)
- [PATCH v9 02/46] target/arm: Improve masking of SCR RES0 bits, Richard Henderson, 2020/06/25
- [PATCH v9 03/46] target/arm: Add support for MTE to SCTLR_ELx, Richard Henderson, 2020/06/25
- [PATCH v9 04/46] target/arm: Add support for MTE to HCR_EL2 and SCR_EL3, Richard Henderson, 2020/06/25
- [PATCH v9 05/46] target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT, Richard Henderson, 2020/06/25
- [PATCH v9 06/46] target/arm: Add DISAS_UPDATE_NOCHAIN, Richard Henderson, 2020/06/25
- [PATCH v9 07/46] target/arm: Add MTE system registers, Richard Henderson, 2020/06/25
- [PATCH v9 08/46] target/arm: Add MTE bits to tb_flags, Richard Henderson, 2020/06/25
- [PATCH v9 09/46] target/arm: Implement the IRG instruction, Richard Henderson, 2020/06/25
- [PATCH v9 10/46] target/arm: Revise decoding for disas_add_sub_imm, Richard Henderson, 2020/06/25
- [PATCH v9 11/46] target/arm: Implement the ADDG, SUBG instructions, Richard Henderson, 2020/06/25
- [PATCH v9 12/46] target/arm: Implement the GMI instruction,
Richard Henderson <=
- [PATCH v9 13/46] target/arm: Implement the SUBP instruction, Richard Henderson, 2020/06/25
- [PATCH v9 14/46] target/arm: Define arm_cpu_do_unaligned_access for user-only, Richard Henderson, 2020/06/25
- [PATCH v9 15/46] target/arm: Implement LDG, STG, ST2G instructions, Richard Henderson, 2020/06/25
- [PATCH v9 16/46] target/arm: Implement the STGP instruction, Richard Henderson, 2020/06/25
- [PATCH v9 18/46] target/arm: Simplify DC_ZVA, Richard Henderson, 2020/06/25
- [PATCH v9 17/46] target/arm: Restrict the values of DCZID.BS under TCG, Richard Henderson, 2020/06/25
- [PATCH v9 20/46] target/arm: Implement the access tag cache flushes, Richard Henderson, 2020/06/25
- [PATCH v9 19/46] target/arm: Implement the LDGM, STGM, STZGM instructions, Richard Henderson, 2020/06/25
- [PATCH v9 21/46] target/arm: Move regime_el to internals.h, Richard Henderson, 2020/06/25
- [PATCH v9 22/46] target/arm: Move regime_tcr to internals.h, Richard Henderson, 2020/06/25