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Re: [PATCH] libqos: pci-pc: use 32-bit write for EJ register


From: Thomas Huth
Subject: Re: [PATCH] libqos: pci-pc: use 32-bit write for EJ register
Date: Wed, 24 Jun 2020 09:46:49 +0200
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0

On 23/06/2020 18.18, Paolo Bonzini wrote:
The memory region ops have min_access_size == 4 so obey it.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
  tests/qtest/libqos/pci-pc.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/qtest/libqos/pci-pc.c b/tests/qtest/libqos/pci-pc.c
index 0bc591d1da..3bb2eb3ba8 100644
--- a/tests/qtest/libqos/pci-pc.c
+++ b/tests/qtest/libqos/pci-pc.c
@@ -186,7 +186,7 @@ void qpci_unplug_acpi_device_test(QTestState *qts, const 
char *id, uint8_t slot)
      g_assert(!qdict_haskey(response, "error"));
      qobject_unref(response);
- qtest_outb(qts, ACPI_PCIHP_ADDR + PCI_EJ_BASE, 1 << slot);
+    qtest_outl(qts, ACPI_PCIHP_ADDR + PCI_EJ_BASE, 1 << slot);
qtest_qmp_eventwait(qts, "DEVICE_DELETED");
  }

I was a little bit afraid that this could cause endianess issues on big endian hosts, but I gave it a try on a s390x machine and it seems to work fine.

Tested-by: Thomas Huth <thuth@redhat.com>




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