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Re: [PULL v2 03/32] riscv: Generalize CPU init routine for the base CPU
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From: |
Alistair Francis |
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Subject: |
Re: [PULL v2 03/32] riscv: Generalize CPU init routine for the base CPU |
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Date: |
Tue, 23 Jun 2020 16:28:39 -0700 |
On Tue, Jun 23, 2020 at 2:08 AM Markus Armbruster <armbru@redhat.com> wrote:
>
> Bin Meng <bmeng.cn@gmail.com> writes:
>
> > Hi Alistair,
> >
> > On Sat, Jun 20, 2020 at 1:09 AM Alistair Francis
> > <alistair.francis@wdc.com> wrote:
> >>
> >> From: Bin Meng <bin.meng@windriver.com>
> >>
> >> There is no need to have two functions that have exactly the same
> >> codes for 32-bit and 64-bit base CPUs.
> >>
> >> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> >> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> >> Message-id: 1591837729-27486-1-git-send-email-bmeng.cn@gmail.com
> >> Message-Id: <1591837729-27486-1-git-send-email-bmeng.cn@gmail.com>
> >
> > I noticed that patches from other people than you have the
> > "Message-id" tags, but your patch [1] does not. Is this intentional?
> >
> > (not sure why we need 2 "Message-id" tags here, with one has <> ?)
>
> We don't. Looks like an accident.
Yeah, that must have been an accident.
>
> > Just want to know what's the best practice here.
>
> The Message-Id tag's purpose is connecting commits back to the mailing
> list. Useful when you want to look up their review later.
>
> To get them into git, maintainers should use git-am -m to apply
> patches. I have
>
> [am]
> messageid = true
>
> in my .gitconfig.
>
> Maintainers may be tempted to use git-rebase or git-cherry-pick instead
> for patches they already have in their local git (such as their own
> patches). No good, because we don't get the Message-Id that way.
Ah, thanks for clarifying that. I was never sure. I'll be sure to not
rebase or cherry-pick my own patches in the future.
Alistair
>
> Patch submissions (as opposed to pull requests) generally do not have
> Message-Id tags in commit messages.
>
> Hope this helps!
>
> >> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> >> ---
> >> target/riscv/cpu.c | 18 +++++-------------
> >> 1 file changed, 5 insertions(+), 13 deletions(-)
> >>
> >
> > [1] https://lists.gnu.org/archive/html/qemu-devel/2020-06/msg06208.html
> >
> > Regards,
> > Bin
>
- [PULL v2 00/32] riscv-to-apply queue, Alistair Francis, 2020/06/19
- [PULL v2 01/32] riscv: Add helper to make NaN-boxing for FP register, Alistair Francis, 2020/06/19
- [PULL v2 14/32] riscv/opentitan: Connect the PLIC device, Alistair Francis, 2020/06/19
- [PULL v2 15/32] riscv/opentitan: Connect the UART device, Alistair Francis, 2020/06/19
- [PULL v2 04/32] riscv: Generalize CPU init routine for the gcsu CPU, Alistair Francis, 2020/06/19
- [PULL v2 06/32] riscv: Keep the CPU init routine names consistent, Alistair Francis, 2020/06/19
- [PULL v2 03/32] riscv: Generalize CPU init routine for the base CPU, Alistair Francis, 2020/06/19
- [PULL v2 19/32] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit, Alistair Francis, 2020/06/19
- [PULL v2 02/32] sifive_e: Support the revB machine, Alistair Francis, 2020/06/19
- [PULL v2 16/32] target/riscv: Use a smaller guess size for no-MMU PMP, Alistair Francis, 2020/06/19
- [PULL v2 05/32] riscv: Generalize CPU init routine for the imacu CPU, Alistair Francis, 2020/06/19
- [PULL v2 08/32] target/riscv: Report errors validating 2nd-stage PTEs, Alistair Francis, 2020/06/19
- [PULL v2 17/32] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions, Alistair Francis, 2020/06/19
- [PULL v2 22/32] hw/riscv: sifive_gpio: Add a new 'ngpio' property, Alistair Francis, 2020/06/19
- [PULL v2 21/32] hw/riscv: sifive_gpio: Clean up the codes, Alistair Francis, 2020/06/19
- [PULL v2 24/32] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs, Alistair Francis, 2020/06/19
- [PULL v2 18/32] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions, Alistair Francis, 2020/06/19