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[PULL 28/32] target/riscv: Rename IBEX CPU init routine
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From: |
Alistair Francis |
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Subject: |
[PULL 28/32] target/riscv: Rename IBEX CPU init routine |
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Date: |
Thu, 18 Jun 2020 23:25:14 -0700 |
From: Bin Meng <bin.meng@windriver.com>
Current IBEX CPU init routine name seems to be too generic.
Since it uses a different reset vector from the generic one,
it merits a dedicated name.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1592268641-7478-2-git-send-email-bmeng.cn@gmail.com
Message-Id: <1592268641-7478-2-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e867766cf0..5f034588ec 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -153,7 +153,7 @@ static void rvxx_imacu_nommu_cpu_init(Object *obj)
#if defined(TARGET_RISCV32)
-static void rv32_imcu_nommu_cpu_init(Object *obj)
+static void rv32_ibex_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RV32 | RVI | RVM | RVC | RVU);
@@ -577,7 +577,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
#if defined(TARGET_RISCV32)
DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_imcu_nommu_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_gcsu_priv1_10_0_cpu_init),
--
2.27.0
- [PULL 08/32] target/riscv: Report errors validating 2nd-stage PTEs, (continued)
- [PULL 08/32] target/riscv: Report errors validating 2nd-stage PTEs, Alistair Francis, 2020/06/19
- [PULL 20/32] hw/riscv: sifive_u: Generate device tree node for OTP, Alistair Francis, 2020/06/19
- [PULL 22/32] hw/riscv: sifive_gpio: Add a new 'ngpio' property, Alistair Francis, 2020/06/19
- [PULL 09/32] target/riscv: Move the hfence instructions to the rvh decode, Alistair Francis, 2020/06/19
- [PULL 23/32] hw/riscv: sifive_u: Hook a GPIO controller, Alistair Francis, 2020/06/19
- [PULL 24/32] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs, Alistair Francis, 2020/06/19
- [PULL 25/32] hw/riscv: sifive_u: Add reset functionality, Alistair Francis, 2020/06/19
- [PULL 26/32] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name, Alistair Francis, 2020/06/19
- [PULL 12/32] hw/char: Initial commit of Ibex UART, Alistair Francis, 2020/06/19
- [PULL 27/32] hw/riscv: sifive_u: Add a new property msel for MSEL pin state, Alistair Francis, 2020/06/19
- [PULL 28/32] target/riscv: Rename IBEX CPU init routine,
Alistair Francis <=
- [PULL 29/32] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004, Alistair Francis, 2020/06/19
- [PULL 30/32] hw/riscv: sifive_u: Support different boot source per MSEL pin state, Alistair Francis, 2020/06/19
- [PULL 31/32] hw/riscv: sifive_u: Sort the SoC memmap table entries, Alistair Francis, 2020/06/19
- [PULL 32/32] hw/riscv: sifive_u: Add a dummy DDR memory controller device, Alistair Francis, 2020/06/19
- Re: [PULL 00/32] riscv-to-apply queue, no-reply, 2020/06/19
- Re: [PULL 00/32] riscv-to-apply queue, Peter Maydell, 2020/06/19