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Re: [PATCH v7 03/42] target/arm: Add support for MTE to SCTLR_ELx


From: Peter Maydell
Subject: Re: [PATCH v7 03/42] target/arm: Add support for MTE to SCTLR_ELx
Date: Thu, 18 Jun 2020 11:52:30 +0100

On Wed, 3 Jun 2020 at 02:13, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This does not attempt to rectify all of the res0 bits, but does
> clear the mte bits when not enabled.  Since there is no high-part
> mapping of SCTLR, aa32 mode cannot write to these bits.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/helper.c | 23 +++++++++++++++++------
>  1 file changed, 17 insertions(+), 6 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 2ec49c1a55..7862bf502d 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -4698,6 +4698,22 @@ static void sctlr_write(CPUARMState *env, const 
> ARMCPRegInfo *ri,
>  {
>      ARMCPU *cpu = env_archcpu(env);
>
> +    if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) {
> +        /* M bit is RAZ/WI for PMSA with no MPU implemented */
> +        value &= ~SCTLR_M;
> +    }
> +
> +    /* ??? Lots of these bits are not implemented.  */
> +
> +    if (ri->state == ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, cpu)) {
> +        if (ri->opc1 == 6) { /* SCTLR_EL3 */
> +            value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA);
> +        } else {
> +            value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF |
> +                       SCTLR_ATA0 | SCTLR_ATA);
> +        }

Doesn't SCTLR_EL2 have the same "no ATA0 and no TCF0" that
SCTLR_EL3 does?

thanks
-- PMM



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