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Re: [PATCH v2 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machin


From: Havard Skinnemoen
Subject: Re: [PATCH v2 00/12] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines
Date: Wed, 17 Jun 2020 22:15:20 -0700

On Wed, Jun 17, 2020 at 8:54 AM Cédric Le Goater <clg@kaod.org> wrote:
Hello,

On 6/12/20 12:30 AM, Havard Skinnemoen wrote:
> This patch series models enough of the Nuvoton NPCM730 and NPCM750 SoCs to boot
> an OpenBMC image built for quanta-gsj. This includes device models for:
>
>   - Global Configuration Registers
>   - Clock Control
>   - Timers
>   - Fuses
>   - Memory Controller
>   - Flash Controller

Do you have a git tree for this patchset ?

Yes, but nothing public. I can set up a github fork if you want.
 
> These modules, along with the existing Cortex A9 CPU cores and built-in
> peripherals, are integrated into a NPCM730 or NPCM750 SoC, which in turn form
> the foundation for the quanta-gsj and npcm750-evb machines, respectively. The
> two SoCs are very similar; the only difference is that NPCM730 is missing some
> peripherals that NPCM750 has, and which are not considered essential for
> datacenter use (e.g. graphics controllers). For more information, see
>
> https://www.nuvoton.com/products/cloud-computing/ibmc/
>
> Both quanta-gsj and npcm750-evb correspond to real boards supported by OpenBMC.
> While this initial series uses a stripped-down kernel for testing, future
> series will be tested using OpenBMC images built from public sources. I'm
> currently putting the finishing touches on flash controller support, which is
> necessary to boot a full OpenBMC image, and will be enabled by the next series.

ok.

It would be nice to be able to download the images from some site
like we do for Aspeed.

It looks like Joel got this covered for gsj. I'll look into setting something up for npcm750-evb.
 

> The patches in this series were developed by Google and reviewed by Nuvoton. We
> will be maintaining the machine and peripheral support together.
>
> The data sheet for these SoCs is not generally available. Please let me know if
> more comments are needed to understand the device behavior.
>
> Changes since v1 (requested by reviewers):
>
>   - Clarify the source of CLK reset values.
>   - Made smpboot a constant byte array, eliinated byte swapping.

I have revived a PPC64 host. We might want to add the swapping back.

OK.

Havard

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