[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 095/100] tcg: Implement 256-bit dup for tcg_gen_gvec_dup_mem
From: |
Richard Henderson |
Subject: |
[PATCH v2 095/100] tcg: Implement 256-bit dup for tcg_gen_gvec_dup_mem |
Date: |
Wed, 17 Jun 2020 21:26:39 -0700 |
We already support duplication of 128-bit blocks. This extends
that support to 256-bit blocks. This will be needed by SVE2.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg-op-gvec.c | 52 ++++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 49 insertions(+), 3 deletions(-)
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 3707c0effb..1b7876bb22 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -1570,12 +1570,10 @@ void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs,
uint32_t aofs,
do_dup(vece, dofs, oprsz, maxsz, NULL, in, 0);
tcg_temp_free_i64(in);
}
- } else {
+ } else if (vece == 4) {
/* 128-bit duplicate. */
- /* ??? Dup to 256-bit vector. */
int i;
- tcg_debug_assert(vece == 4);
tcg_debug_assert(oprsz >= 16);
if (TCG_TARGET_HAS_v128) {
TCGv_vec in = tcg_temp_new_vec(TCG_TYPE_V128);
@@ -1601,6 +1599,54 @@ void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs,
uint32_t aofs,
if (oprsz < maxsz) {
expand_clr(dofs + oprsz, maxsz - oprsz);
}
+ } else if (vece == 5) {
+ /* 256-bit duplicate. */
+ int i;
+
+ tcg_debug_assert(oprsz >= 32);
+ tcg_debug_assert(oprsz % 32 == 0);
+ if (TCG_TARGET_HAS_v256) {
+ TCGv_vec in = tcg_temp_new_vec(TCG_TYPE_V256);
+
+ tcg_gen_ld_vec(in, cpu_env, aofs);
+ for (i = 0; i < oprsz; i += 32) {
+ tcg_gen_st_vec(in, cpu_env, dofs + i);
+ }
+ tcg_temp_free_vec(in);
+ } else if (TCG_TARGET_HAS_v128) {
+ TCGv_vec in0 = tcg_temp_new_vec(TCG_TYPE_V128);
+ TCGv_vec in1 = tcg_temp_new_vec(TCG_TYPE_V128);
+
+ tcg_gen_ld_vec(in0, cpu_env, aofs);
+ tcg_gen_ld_vec(in1, cpu_env, aofs + 16);
+ for (i = 0; i < oprsz; i += 32) {
+ tcg_gen_st_vec(in0, cpu_env, dofs + i);
+ tcg_gen_st_vec(in1, cpu_env, dofs + i + 16);
+ }
+ tcg_temp_free_vec(in0);
+ tcg_temp_free_vec(in1);
+ } else {
+ TCGv_i64 in[4];
+ int j;
+
+ for (j = 0; j < 4; ++j) {
+ in[j] = tcg_temp_new_i64();
+ tcg_gen_ld_i64(in[j], cpu_env, aofs + j * 8);
+ }
+ for (i = 0; i < oprsz; i += 32) {
+ for (j = 0; j < 4; ++j) {
+ tcg_gen_st_i64(in[j], cpu_env, dofs + i + j * 8);
+ }
+ }
+ for (j = 0; j < 4; ++j) {
+ tcg_temp_free_i64(in[j]);
+ }
+ }
+ if (oprsz < maxsz) {
+ expand_clr(dofs + oprsz, maxsz - oprsz);
+ }
+ } else {
+ g_assert_not_reached();
}
}
--
2.25.1
- [PATCH v2 084/100] target/arm: Implement SVE mixed sign dot product (indexed), (continued)
- [PATCH v2 084/100] target/arm: Implement SVE mixed sign dot product (indexed), Richard Henderson, 2020/06/18
- [PATCH v2 087/100] target/arm: Implement SVE2 crypto destructive binary operations, Richard Henderson, 2020/06/18
- [PATCH v2 086/100] target/arm: Implement SVE2 crypto unary operations, Richard Henderson, 2020/06/18
- [PATCH v2 088/100] target/arm: Implement SVE2 crypto constructive binary operations, Richard Henderson, 2020/06/18
- [PATCH v2 085/100] target/arm: Implement SVE mixed sign dot product, Richard Henderson, 2020/06/18
- [PATCH v2 089/100] target/arm: Implement SVE2 TBL, TBX, Richard Henderson, 2020/06/18
- [PATCH v2 090/100] target/arm: Implement SVE2 FCVTNT, Richard Henderson, 2020/06/18
- [PATCH v2 091/100] target/arm: Implement SVE2 FCVTLT, Richard Henderson, 2020/06/18
- [PATCH v2 092/100] target/arm: Implement SVE2 FCVTXNT, FCVTX, Richard Henderson, 2020/06/18
- [PATCH v2 093/100] softfloat: Add float16_is_normal, Richard Henderson, 2020/06/18
- [PATCH v2 095/100] tcg: Implement 256-bit dup for tcg_gen_gvec_dup_mem,
Richard Henderson <=
- [PATCH v2 094/100] target/arm: Implement SVE2 FLOGB, Richard Henderson, 2020/06/18
- [PATCH v2 096/100] target/arm: Share table of sve load functions, Richard Henderson, 2020/06/18
- [PATCH v2 099/100] target/arm: Implement SVE2 bitwise shift immediate, Richard Henderson, 2020/06/18
- [PATCH v2 097/100] target/arm: Implement SVE2 LD1RO, Richard Henderson, 2020/06/18
- [PATCH v2 098/100] target/arm: Implement 128-bit ZIP, UZP, TRN, Richard Henderson, 2020/06/18
- [PATCH v2 100/100] target/arm: Implement SVE2 fp multiply-add long, Richard Henderson, 2020/06/18
- Re: [PATCH v2 000/100] target/arm: Implement SVE2, no-reply, 2020/06/18
- Re: [PATCH v2 000/100] target/arm: Implement SVE2, no-reply, 2020/06/18