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[PATCH v2 055/100] target/arm: Implement SVE2 RADDHNB, RADDHNT
From: |
Richard Henderson |
Subject: |
[PATCH v2 055/100] target/arm: Implement SVE2 RADDHNB, RADDHNT |
Date: |
Wed, 17 Jun 2020 21:25:59 -0700 |
From: Stephen Long <steplong@quicinc.com>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Message-Id: <20200417162231.10374-3-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Fix round bit type (laurent desnogues)
---
target/arm/helper-sve.h | 8 ++++++++
target/arm/sve.decode | 2 ++
target/arm/sve_helper.c | 10 ++++++++++
target/arm/translate-sve.c | 2 ++
4 files changed, 22 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index 84281e3f9d..7627e0cd5f 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -2029,6 +2029,14 @@ DEF_HELPER_FLAGS_4(sve2_addhnt_h, TCG_CALL_NO_RWG, void,
ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_addhnt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve2_addhnt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_raddhnb_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_raddhnb_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_raddhnb_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(sve2_raddhnt_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_raddhnt_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_raddhnt_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_5(sve2_match_ppzz_b, TCG_CALL_NO_RWG,
i32, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_match_ppzz_h, TCG_CALL_NO_RWG,
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index af9e87e88d..a33825066c 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1324,6 +1324,8 @@ UQRSHRNT 01000101 .. 1 ..... 00 1111 ..... .....
@rd_rn_tszimm_shr
ADDHNB 01000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm
ADDHNT 01000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm
+RADDHNB 01000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm
+RADDHNT 01000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm
### SVE2 Character Match
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 7f3dd2dfdb..281a680134 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -2114,6 +2114,7 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t
desc) \
}
#define DO_ADDHN(N, M, SH) ((N + M) >> SH)
+#define DO_RADDHN(N, M, SH) ((N + M + ((__typeof(N))1 << (SH - 1))) >> SH)
DO_BINOPNB(sve2_addhnb_h, uint16_t, uint8_t, 8, DO_ADDHN)
DO_BINOPNB(sve2_addhnb_s, uint32_t, uint16_t, 16, DO_ADDHN)
@@ -2123,6 +2124,15 @@ DO_BINOPNT(sve2_addhnt_h, uint16_t, uint8_t, 8, H1_2,
H1, DO_ADDHN)
DO_BINOPNT(sve2_addhnt_s, uint32_t, uint16_t, 16, H1_4, H1_2, DO_ADDHN)
DO_BINOPNT(sve2_addhnt_d, uint64_t, uint32_t, 32, , H1_4, DO_ADDHN)
+DO_BINOPNB(sve2_raddhnb_h, uint16_t, uint8_t, 8, DO_RADDHN)
+DO_BINOPNB(sve2_raddhnb_s, uint32_t, uint16_t, 16, DO_RADDHN)
+DO_BINOPNB(sve2_raddhnb_d, uint64_t, uint32_t, 32, DO_RADDHN)
+
+DO_BINOPNT(sve2_raddhnt_h, uint16_t, uint8_t, 8, H1_2, H1, DO_RADDHN)
+DO_BINOPNT(sve2_raddhnt_s, uint32_t, uint16_t, 16, H1_4, H1_2, DO_RADDHN)
+DO_BINOPNT(sve2_raddhnt_d, uint64_t, uint32_t, 32, , H1_4, DO_RADDHN)
+
+#undef DO_RADDHN
#undef DO_ADDHN
#undef DO_BINOPNB
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 7dc30ed1bd..7e3ba2e4f7 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -7035,6 +7035,8 @@ static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a)
\
DO_SVE2_ZZZ_NARROW(ADDHNB, addhnb)
DO_SVE2_ZZZ_NARROW(ADDHNT, addhnt)
+DO_SVE2_ZZZ_NARROW(RADDHNB, raddhnb)
+DO_SVE2_ZZZ_NARROW(RADDHNT, raddhnt)
static bool do_sve2_ppzz_flags(DisasContext *s, arg_rprr_esz *a,
gen_helper_gvec_flags_4 *fn)
--
2.25.1
- [PATCH v2 043/100] target/arm: Implement SVE2 UQSHRN, UQRSHRN, (continued)
- [PATCH v2 043/100] target/arm: Implement SVE2 UQSHRN, UQRSHRN, Richard Henderson, 2020/06/18
- [PATCH v2 044/100] target/arm: Implement SVE2 SQSHRN, SQRSHRN, Richard Henderson, 2020/06/18
- [PATCH v2 045/100] target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS, Richard Henderson, 2020/06/18
- [PATCH v2 046/100] target/arm: Implement SVE2 WHILERW, WHILEWR, Richard Henderson, 2020/06/18
- [PATCH v2 048/100] target/arm: Implement SVE2 MATCH, NMATCH, Richard Henderson, 2020/06/18
- [PATCH v2 047/100] target/arm: Implement SVE2 bitwise ternary operations, Richard Henderson, 2020/06/18
- [PATCH v2 049/100] target/arm: Implement SVE2 saturating multiply-add long, Richard Henderson, 2020/06/18
- [PATCH v2 050/100] target/arm: Generalize inl_qrdmlah_* helper functions, Richard Henderson, 2020/06/18
- [PATCH v2 051/100] target/arm: Implement SVE2 saturating multiply-add high, Richard Henderson, 2020/06/18
- [PATCH v2 053/100] target/arm: Implement SVE2 complex integer multiply-add, Richard Henderson, 2020/06/18
- [PATCH v2 055/100] target/arm: Implement SVE2 RADDHNB, RADDHNT,
Richard Henderson <=
- [PATCH v2 052/100] target/arm: Implement SVE2 integer multiply-add long, Richard Henderson, 2020/06/18
- [PATCH v2 054/100] target/arm: Implement SVE2 ADDHNB, ADDHNT, Richard Henderson, 2020/06/18
- [PATCH v2 056/100] target/arm: Implement SVE2 SUBHNB, SUBHNT, Richard Henderson, 2020/06/18
- [PATCH v2 059/100] target/arm: Implement SVE2 XAR, Richard Henderson, 2020/06/18
- [PATCH v2 057/100] target/arm: Implement SVE2 RSUBHNB, RSUBHNT, Richard Henderson, 2020/06/18
- [PATCH v2 058/100] target/arm: Implement SVE2 HISTCNT, HISTSEG, Richard Henderson, 2020/06/18
- [PATCH v2 061/100] target/arm: Implement SVE2 gather load insns, Richard Henderson, 2020/06/18
- [PATCH v2 063/100] target/arm: Implement SVE2 SPLICE, EXT, Richard Henderson, 2020/06/18
- [PATCH v2 060/100] target/arm: Implement SVE2 scatter store insns, Richard Henderson, 2020/06/18
- [PATCH v2 062/100] target/arm: Implement SVE2 FMMLA, Richard Henderson, 2020/06/18