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[PATCH v2 036/100] target/arm: Implement SVE2 bitwise shift right and ac
From: |
Richard Henderson |
Subject: |
[PATCH v2 036/100] target/arm: Implement SVE2 bitwise shift right and accumulate |
Date: |
Wed, 17 Jun 2020 21:25:40 -0700 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/sve.decode | 8 ++++++++
target/arm/translate-sve.c | 34 ++++++++++++++++++++++++++++++++++
2 files changed, 42 insertions(+)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index f4f0c2ade6..7783e9f0d3 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1253,3 +1253,11 @@ UABALT 01000101 .. 0 ..... 1100 11 ..... .....
@rda_rn_rm
# ADC and SBC decoded via size in helper dispatch.
ADCLB 01000101 .. 0 ..... 11010 0 ..... ..... @rda_rn_rm
ADCLT 01000101 .. 0 ..... 11010 1 ..... ..... @rda_rn_rm
+
+## SVE2 bitwise shift right and accumulate
+
+# TODO: Use @rda and %reg_movprfx here.
+SSRA 01000101 .. 0 ..... 1110 00 ..... ..... @rd_rn_tszimm_shr
+USRA 01000101 .. 0 ..... 1110 01 ..... ..... @rd_rn_tszimm_shr
+SRSRA 01000101 .. 0 ..... 1110 10 ..... ..... @rd_rn_tszimm_shr
+URSRA 01000101 .. 0 ..... 1110 11 ..... ..... @rd_rn_tszimm_shr
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 9131b6d546..3dcc67740f 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -5960,3 +5960,37 @@ static bool trans_ADCLT(DisasContext *s, arg_rrrr_esz *a)
{
return do_adcl(s, a, true);
}
+
+static bool do_sve2_fn2i(DisasContext *s, arg_rri_esz *a, GVecGen2iFn *fn)
+{
+ if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
+ return false;
+ }
+ if (sve_access_check(s)) {
+ unsigned vsz = vec_full_reg_size(s);
+ unsigned rd_ofs = vec_full_reg_offset(s, a->rd);
+ unsigned rn_ofs = vec_full_reg_offset(s, a->rn);
+ fn(a->esz, rd_ofs, rn_ofs, a->imm, vsz, vsz);
+ }
+ return true;
+}
+
+static bool trans_SSRA(DisasContext *s, arg_rri_esz *a)
+{
+ return do_sve2_fn2i(s, a, gen_gvec_ssra);
+}
+
+static bool trans_USRA(DisasContext *s, arg_rri_esz *a)
+{
+ return do_sve2_fn2i(s, a, gen_gvec_usra);
+}
+
+static bool trans_SRSRA(DisasContext *s, arg_rri_esz *a)
+{
+ return do_sve2_fn2i(s, a, gen_gvec_srsra);
+}
+
+static bool trans_URSRA(DisasContext *s, arg_rri_esz *a)
+{
+ return do_sve2_fn2i(s, a, gen_gvec_ursra);
+}
--
2.25.1
- [PATCH v2 024/100] target/arm: Implement SVE2 integer add/subtract long, (continued)
- [PATCH v2 024/100] target/arm: Implement SVE2 integer add/subtract long, Richard Henderson, 2020/06/18
- [PATCH v2 025/100] target/arm: Implement SVE2 integer add/subtract interleaved long, Richard Henderson, 2020/06/18
- [PATCH v2 026/100] target/arm: Implement SVE2 integer add/subtract wide, Richard Henderson, 2020/06/18
- [PATCH v2 029/100] target/arm: Tidy SVE tszimm shift formats, Richard Henderson, 2020/06/18
- [PATCH v2 027/100] target/arm: Implement SVE2 integer multiply long, Richard Henderson, 2020/06/18
- [PATCH v2 028/100] target/arm: Implement PMULLB and PMULLT, Richard Henderson, 2020/06/18
- [PATCH v2 030/100] target/arm: Implement SVE2 bitwise shift left long, Richard Henderson, 2020/06/18
- [PATCH v2 033/100] target/arm: Implement SVE2 complex integer add, Richard Henderson, 2020/06/18
- [PATCH v2 034/100] target/arm: Implement SVE2 integer absolute difference and accumulate long, Richard Henderson, 2020/06/18
- [PATCH v2 035/100] target/arm: Implement SVE2 integer add/subtract long with carry, Richard Henderson, 2020/06/18
- [PATCH v2 036/100] target/arm: Implement SVE2 bitwise shift right and accumulate,
Richard Henderson <=
- [PATCH v2 031/100] target/arm: Implement SVE2 bitwise exclusive-or interleaved, Richard Henderson, 2020/06/18
- [PATCH v2 032/100] target/arm: Implement SVE2 bitwise permute, Richard Henderson, 2020/06/18
- [PATCH v2 037/100] target/arm: Implement SVE2 bitwise shift and insert, Richard Henderson, 2020/06/18
- [PATCH v2 038/100] target/arm: Implement SVE2 integer absolute difference and accumulate, Richard Henderson, 2020/06/18
- [PATCH v2 039/100] target/arm: Implement SVE2 saturating extract narrow, Richard Henderson, 2020/06/18
- [PATCH v2 040/100] target/arm: Implement SVE2 floating-point pairwise, Richard Henderson, 2020/06/18
- [PATCH v2 041/100] target/arm: Implement SVE2 SHRN, RSHRN, Richard Henderson, 2020/06/18
- [PATCH v2 042/100] target/arm: Implement SVE2 SQSHRUN, SQRSHRUN, Richard Henderson, 2020/06/18
- [PATCH v2 043/100] target/arm: Implement SVE2 UQSHRN, UQRSHRN, Richard Henderson, 2020/06/18
- [PATCH v2 044/100] target/arm: Implement SVE2 SQSHRN, SQRSHRN, Richard Henderson, 2020/06/18