[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 075/115] target/i386: define a new MSR based feature word - FEAT_P
From: |
Paolo Bonzini |
Subject: |
[PULL 075/115] target/i386: define a new MSR based feature word - FEAT_PERF_CAPABILITIES |
Date: |
Thu, 11 Jun 2020 15:44:09 -0400 |
From: Like Xu <like.xu@linux.intel.com>
The Perfmon and Debug Capability MSR named IA32_PERF_CAPABILITIES is
a feature-enumerating MSR, which only enumerates the feature full-width
write (via bit 13) by now which indicates the processor supports IA32_A_PMCx
interface for updating bits 32 and above of IA32_PMCx.
The existence of MSR IA32_PERF_CAPABILITIES is enumerated by CPUID.1:ECX[15].
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Richard Henderson <rth@twiddle.net>
Cc: Eduardo Habkost <ehabkost@redhat.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: qemu-devel@nongnu.org
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Message-Id: <20200529074347.124619-5-like.xu@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/cpu.c | 23 +++++++++++++++++++++++
target/i386/cpu.h | 3 +++
target/i386/kvm.c | 20 ++++++++++++++++++++
3 files changed, 46 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e89d9fa894..2d3b8d5dea 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1139,6 +1139,22 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS]
= {
.index = MSR_IA32_CORE_CAPABILITY,
},
},
+ [FEAT_PERF_CAPABILITIES] = {
+ .type = MSR_FEATURE_WORD,
+ .feat_names = {
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, "full-width-write", NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ },
+ .msr = {
+ .index = MSR_IA32_PERF_CAPABILITIES,
+ },
+ },
[FEAT_VMX_PROCBASED_CTLS] = {
.type = MSR_FEATURE_WORD,
@@ -1316,6 +1332,10 @@ static FeatureDep feature_dependencies[] = {
.from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY },
.to = { FEAT_CORE_CAPABILITY, ~0ull },
},
+ {
+ .from = { FEAT_1_ECX, CPUID_EXT_PDCM },
+ .to = { FEAT_PERF_CAPABILITIES, ~0ull },
+ },
{
.from = { FEAT_1_ECX, CPUID_EXT_VMX },
.to = { FEAT_VMX_PROCBASED_CTLS, ~0ull },
@@ -5488,6 +5508,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
*ebx |= (cs->nr_cores * cs->nr_threads) << 16;
*edx |= CPUID_HT;
}
+ if (!cpu->enable_pmu) {
+ *ecx &= ~CPUID_EXT_PDCM;
+ }
break;
case 2:
/* cache info: needed for Pentium Pro compatibility */
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 100476ee89..c2b8bdcbde 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -356,6 +356,8 @@ typedef enum X86Seg {
#define MSR_IA32_ARCH_CAPABILITIES 0x10a
#define ARCH_CAP_TSX_CTRL_MSR (1<<7)
+#define MSR_IA32_PERF_CAPABILITIES 0x345
+
#define MSR_IA32_TSX_CTRL 0x122
#define MSR_IA32_TSCDEADLINE 0x6e0
@@ -529,6 +531,7 @@ typedef enum FeatureWord {
FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
FEAT_ARCH_CAPABILITIES,
FEAT_CORE_CAPABILITY,
+ FEAT_PERF_CAPABILITIES,
FEAT_VMX_PROCBASED_CTLS,
FEAT_VMX_SECONDARY_CTLS,
FEAT_VMX_PINBASED_CTLS,
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index ef2e0a81dd..b3c13cb898 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -110,6 +110,7 @@ static bool has_msr_core_capabs;
static bool has_msr_vmx_vmfunc;
static bool has_msr_ucode_rev;
static bool has_msr_vmx_procbased_ctls2;
+static bool has_msr_perf_capabs;
static uint32_t has_architectural_pmu_version;
static uint32_t num_architectural_pmu_gp_counters;
@@ -2033,6 +2034,9 @@ static int kvm_get_supported_msrs(KVMState *s)
case MSR_IA32_CORE_CAPABILITY:
has_msr_core_capabs = true;
break;
+ case MSR_IA32_PERF_CAPABILITIES:
+ has_msr_perf_capabs = true;
+ break;
case MSR_IA32_VMX_VMFUNC:
has_msr_vmx_vmfunc = true;
break;
@@ -2649,6 +2653,18 @@ static void kvm_msr_entry_add_vmx(X86CPU *cpu,
FeatureWordArray f)
VMCS12_MAX_FIELD_INDEX << 1);
}
+static void kvm_msr_entry_add_perf(X86CPU *cpu, FeatureWordArray f)
+{
+ uint64_t kvm_perf_cap =
+ kvm_arch_get_supported_msr_feature(kvm_state,
+ MSR_IA32_PERF_CAPABILITIES);
+
+ if (kvm_perf_cap) {
+ kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES,
+ kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]);
+ }
+}
+
static int kvm_buf_set_msrs(X86CPU *cpu)
{
int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
@@ -2681,6 +2697,10 @@ static void kvm_init_msrs(X86CPU *cpu)
env->features[FEAT_CORE_CAPABILITY]);
}
+ if (has_msr_perf_capabs && cpu->enable_pmu) {
+ kvm_msr_entry_add_perf(cpu, env->features);
+ }
+
if (has_msr_ucode_rev) {
kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev);
}
--
2.26.2
- [PULL 022/115] vmbus: add infrastructure to save/load vmbus requests, (continued)
- [PULL 022/115] vmbus: add infrastructure to save/load vmbus requests, Paolo Bonzini, 2020/06/11
- [PULL 057/115] exec: Propagate cpu_memory_rw_debug() error, Paolo Bonzini, 2020/06/11
- [PULL 031/115] hw/i386/vmport: Introduce vmport.h, Paolo Bonzini, 2020/06/11
- [PULL 047/115] i386/kvm: fix a use-after-free when vcpu plug/unplug, Paolo Bonzini, 2020/06/11
- [PULL 040/115] qom: remove index from object_resolve_abs_path(), Paolo Bonzini, 2020/06/11
- [PULL 070/115] chardev/char-socket: Properly make qio connections non blocking, Paolo Bonzini, 2020/06/11
- [PULL 072/115] hw/i386/amd_iommu: Fix the reserved bits definition of IOMMU commands, Paolo Bonzini, 2020/06/11
- [PULL 068/115] KVM: Pass EventNotifier into kvm_irqchip_assign_irqfd, Paolo Bonzini, 2020/06/11
- [PULL 076/115] util/oslib: Returns the real thread identifier on FreeBSD and NetBSD, Paolo Bonzini, 2020/06/11
- [PULL 079/115] configure: Do not ignore malloc value, Paolo Bonzini, 2020/06/11
- [PULL 075/115] target/i386: define a new MSR based feature word - FEAT_PERF_CAPABILITIES,
Paolo Bonzini <=
- [PULL 074/115] i386: Remove unused define's from hax and hvf, Paolo Bonzini, 2020/06/11
- [PULL 077/115] memory: Make 'info mtree' not display disabled regions by default, Paolo Bonzini, 2020/06/11
- [PULL 078/115] qemu/thread: Mark qemu_thread_exit() with 'noreturn' attribute, Paolo Bonzini, 2020/06/11
- [PULL 071/115] tests: machine-none-test: Enable MicroBlaze testing, Paolo Bonzini, 2020/06/11
- [PULL 050/115] megasas: use unsigned type for positive numeric fields, Paolo Bonzini, 2020/06/11
- [PULL 084/115] sysemu/tcg: Only declare tcg_allowed when TCG is available, Paolo Bonzini, 2020/06/11
- [PULL 082/115] target/i386: correct fix for pcmpxstrx substring search, Paolo Bonzini, 2020/06/11
- [PULL 081/115] target/i386: fix IEEE x87 floating-point exception raising, Paolo Bonzini, 2020/06/11
- [PULL 089/115] i386: hvf: Drop unused variable, Paolo Bonzini, 2020/06/11
- [PULL 092/115] i386: hvf: Drop fetch_rip from HVFX86EmulatorState, Paolo Bonzini, 2020/06/11