Re: [PATCH] target/arm: Init GIC CPU IF regs for A15/A7

[Adam Lackorzynski]

On Mon Jun 01, 2020 at 13:36:13 +0100, Peter Maydell wrote:
> On Sat, 30 May 2020 at 00:07, Adam Lackorzynski <adam@l4re.org> wrote:
> >
> > Initialize the CPU interface registers also
> > for Cortex-A15 and Cortex-A7 CPU models, in
> > the same way as done for 64bit CPU models.
> > This fixes usage of GICv3 in virtualization
> > contexts in 32bit configurations.
> >
> > Signed-off-by: Adam Lackorzynski <adam@l4re.org>
> 
> Hi; I'm confused by this patch. The Cortex-A15 and Cortex-A7
> do not have or support the GICv3, so why would we need
> to set GICv3-specific settings for them?
> 
> We're probably missing a sanity-check somewhere
> to forbid user attempts to use non-GICv3 CPUs with
> the GICv3.

Indeed that's another option. Besides that A15+GICv3 currently just
works with this.
So I guess the alternative is to switch to 32bit from EL3 when using an A57?


Thanks,
Adam