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[RISU PATCH v2 17/22] sve2.risu: Add patterns for multiply (indexed) ops
From: |
Stephen Long |
Subject: |
[RISU PATCH v2 17/22] sve2.risu: Add patterns for multiply (indexed) ops |
Date: |
Thu, 21 May 2020 12:25:06 -0700 |
Signed-off-by: Stephen Long <address@hidden>
---
sve2.risu | 86 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 86 insertions(+)
diff --git a/sve2.risu b/sve2.risu
index 8602059..1bcbd93 100755
--- a/sve2.risu
+++ b/sve2.risu
@@ -66,6 +66,92 @@ SQDMLSLT A64_V 01000100 size:2 0 zm:5 0110 11 zn:5
zda:5 \
SQRDMLAH A64_V 01000100 size:2 0 zm:5 01110 0 zn:5 zda:5
SQRDMLSH A64_V 01000100 size:2 0 zm:5 01110 1 zn:5 zda:5
+# Multiply (Indexed)
+## integer multiply-add (indexed)
+MLA_H A64_V 01000100 0 i3h:1 1 i3l:2 zm:3 00001 0 zn:5 zda:5
+MLS_H A64_V 01000100 0 i3h:1 1 i3l:2 zm:3 00001 1 zn:5 zda:5
+
+MLA_S A64_V 01000100 1 0 1 i2:2 zm:3 00001 0 zn:5 zda:5
+MLS_S A64_V 01000100 1 0 1 i2:2 zm:3 00001 1 zn:5 zda:5
+
+MLA_D A64_V 01000100 1 1 1 i1:1 zm:4 00001 0 zn:5 zda:5
+MLS_D A64_V 01000100 1 1 1 i1:1 zm:4 00001 1 zn:5 zda:5
+## saturating multiply-add high (indexed)
+SQRDMLAH_H A64_V 01000100 0 i3h:1 1 i3l:2 zm:3 00010 0 zn:5 zda:5
+SQRDMLSH_H A64_V 01000100 0 i3h:1 1 i3l:2 zm:3 00010 1 zn:5 zda:5
+
+SQRDMLAH_S A64_V 01000100 1 0 1 i2:2 zm:3 00010 0 zn:5 zda:5
+SQRDMLSH_S A64_V 01000100 1 0 1 i2:2 zm:3 00010 1 zn:5 zda:5
+
+SQRDMLAH_D A64_V 01000100 1 1 1 i1:1 zm:4 00010 0 zn:5 zda:5
+SQRDMLSH_D A64_V 01000100 1 1 1 i1:1 zm:4 00010 1 zn:5 zda:5
+## saturating multiply-add (indexed)
+SQDMLALB_S A64_V 01000100 1 0 1 i3h:2 zm:3 001 0 i3l:1 0 zn:5 zda:5
+SQDMLALT_S A64_V 01000100 1 0 1 i3h:2 zm:3 001 0 i3l:1 1 zn:5 zda:5
+SQDMLSLB_S A64_V 01000100 1 0 1 i3h:2 zm:3 001 1 i3l:1 0 zn:5 zda:5
+SQDMLSLT_S A64_V 01000100 1 0 1 i3h:2 zm:3 001 1 i3l:1 1 zn:5 zda:5
+
+SQDMLALB_D A64_V 01000100 1 1 1 i2h:1 zm:4 001 0 i2l:1 0 zn:5 zda:5
+SQDMLALT_D A64_V 01000100 1 1 1 i2h:1 zm:4 001 0 i2l:1 1 zn:5 zda:5
+SQDMLSLB_D A64_V 01000100 1 1 1 i2h:1 zm:4 001 1 i2l:1 0 zn:5 zda:5
+SQDMLSLT_D A64_V 01000100 1 1 1 i2h:1 zm:4 001 1 i2l:1 1 zn:5 zda:5
+## complex integer dot product (indexed)
+CDOT_S A64_V 01000100 1 0 1 i2:2 zm:3 0100 rot:2 zn:5 zda:5
+CDOT_D A64_V 01000100 1 1 1 i1:1 zm:4 0100 rot:2 zn:5 zda:5
+## complex integer multiply-add (indexed)
+CMLA_S A64_V 01000100 1 0 1 i2:2 zm:3 0110 rot:2 zn:5 zda:5
+CMLA_D A64_V 01000100 1 1 1 i1:1 zm:4 0110 rot:2 zn:5 zda:5
+## complex saturating multiply-add (indexed)
+SQRDCMLAH_H A64_V 01000100 1 0 1 i2:2 zm:3 0111 rot:2 zn:5 zda:5
+SQRDCMLAH_S A64_V 01000100 1 1 1 i1:1 zm:4 0111 rot:2 zn:5 zda:5
+## integer multiply-add long (indexed)
+SMLALB_S A64_V 01000100 101 i3h:2 zm:3 1000 i3l:1 0 zn:5 zda:5
+SMLALT_S A64_V 01000100 101 i3h:2 zm:3 1000 i3l:1 1 zn:5 zda:5
+UMLALB_S A64_V 01000100 101 i3h:2 zm:3 1001 i3l:1 0 zn:5 zda:5
+UMLALT_S A64_V 01000100 101 i3h:2 zm:3 1001 i3l:1 1 zn:5 zda:5
+SMLSLB_S A64_V 01000100 101 i3h:2 zm:3 1010 i3l:1 0 zn:5 zda:5
+SMLSLT_S A64_V 01000100 101 i3h:2 zm:3 1010 i3l:1 1 zn:5 zda:5
+UMLSLB_S A64_V 01000100 101 i3h:2 zm:3 1011 i3l:1 0 zn:5 zda:5
+UMLSLT_S A64_V 01000100 101 i3h:2 zm:3 1011 i3l:1 1 zn:5 zda:5
+
+SMLALB_D A64_V 01000100 111 i2h:1 zm:4 1000 i2l:1 0 zn:5 zda:5
+SMLALT_D A64_V 01000100 111 i2h:1 zm:4 1000 i2l:1 1 zn:5 zda:5
+UMLALB_D A64_V 01000100 111 i2h:1 zm:4 1001 i2l:1 0 zn:5 zda:5
+UMLALT_D A64_V 01000100 111 i2h:1 zm:4 1001 i2l:1 1 zn:5 zda:5
+SMLSLB_D A64_V 01000100 111 i2h:1 zm:4 1010 i2l:1 0 zn:5 zda:5
+SMLSLT_D A64_V 01000100 111 i2h:1 zm:4 1010 i2l:1 1 zn:5 zda:5
+UMLSLB_D A64_V 01000100 111 i2h:1 zm:4 1011 i2l:1 0 zn:5 zda:5
+UMLSLT_D A64_V 01000100 111 i2h:1 zm:4 1011 i2l:1 1 zn:5 zda:5
+## integer multiply long (indexed)
+SMULLB_S A64_V 01000100 101 i3h:2 zm:3 1100 i3l:1 0 zn:5 zd:5
+SMULLT_S A64_V 01000100 101 i3h:2 zm:3 1100 i3l:1 1 zn:5 zd:5
+UMULLB_S A64_V 01000100 101 i3h:2 zm:3 1101 i3l:1 0 zn:5 zd:5
+UMULLT_S A64_V 01000100 101 i3h:2 zm:3 1101 i3l:1 1 zn:5 zd:5
+
+SMULLB_D A64_V 01000100 111 i2h:1 zm:4 1100 i2l:1 0 zn:5 zd:5
+SMULLT_D A64_V 01000100 111 i2h:1 zm:4 1100 i2l:1 1 zn:5 zd:5
+UMULLB_D A64_V 01000100 111 i2h:1 zm:4 1101 i2l:1 0 zn:5 zd:5
+UMULLT_D A64_V 01000100 111 i2h:1 zm:4 1101 i2l:1 1 zn:5 zd:5
+## saturating multiply (indexed)
+SQDMULLB_S A64_V 01000100 101 i3h:2 zm:3 1110 i3l:1 0 zn:5 zd:5
+SQDMULLT_S A64_V 01000100 101 i3h:2 zm:3 1110 i3l:1 1 zn:5 zd:5
+
+SQDMULLB_D A64_V 01000100 111 i2h:1 zm:4 1110 i2l:1 0 zn:5 zd:5
+SQDMULLT_D A64_V 01000100 111 i2h:1 zm:4 1110 i2l:1 1 zn:5 zd:5
+## saturating multiply high (indexed)
+SQDMULH_H A64_V 01000100 0 i3h:1 1 i3l:2 zm:3 11110 0 zn:5 zd:5
+SQRDMULH_H A64_V 01000100 0 i3h:1 1 i3l:2 zm:3 11110 1 zn:5 zd:5
+
+SQDMULH_S A64_V 01000100 101 i2:2 zm:3 11110 0 zn:5 zd:5
+SQRDMULH_S A64_V 01000100 101 i2:2 zm:3 11110 1 zn:5 zd:5
+
+SQDMULH_D A64_V 01000100 111 i1:1 zm:4 11110 0 zn:5 zd:5
+SQRDMULH_D A64_V 01000100 111 i1:1 zm:4 11110 1 zn:5 zd:5
+## integer multiply (indexed)
+MUL_H A64_V 01000100 0 i3h:1 1 i3l:2 zm:3 111110 zn:5 zd:5
+MUL_S A64_V 01000100 101 i2:2 zm:3 111110 zn:5 zd:5
+MUL_D A64_V 01000100 111 i1:1 zm:4 111110 zn:5 zd:5
+
# Integer Multiply (Unpredicated)
## integer multiply vectors (unpredicated)
MUL A64_V 00000100 size:2 1 zm:5 0110 00 zn:5 zd:5
--
2.25.1
- [RISU PATCH v2 12/22] sve2.risu: Add patterns for fp convert precision odd elems insns, (continued)
- [RISU PATCH v2 12/22] sve2.risu: Add patterns for fp convert precision odd elems insns, Stephen Long, 2020/05/21
- [RISU PATCH v2 13/22] sve2.risu: Add patterns for bitwise logical (unpredicated) ops, Stephen Long, 2020/05/21
- [RISU PATCH v2 18/22] sve2.risu: Add patterns for permute vector ops, Stephen Long, 2020/05/21
- [RISU PATCH v2 15/22] sve2.risu: Add patterns for table lookup insns, Stephen Long, 2020/05/21
- [RISU PATCH v2 02/22] sve2.risu: Add patterns for integer multiply (unpredicated) ops, Stephen Long, 2020/05/21
- [RISU PATCH v2 01/22] sve2.risu: Add patterns for floating-point pairwise ops, Stephen Long, 2020/05/21
- [RISU PATCH v2 03/22] sve2.risu: Add patterns for integer (predicated) ops, Stephen Long, 2020/05/21
- [RISU PATCH v2 10/22] sve2.risu: Add patterns for crypto operations, Stephen Long, 2020/05/21
- [RISU PATCH v2 05/22] sve2.risu: Add patterns for misc ops, Stephen Long, 2020/05/21
- [RISU PATCH v2 14/22] sve2.risu: Add patterns for fp unary ops (predicated), Stephen Long, 2020/05/21
- [RISU PATCH v2 17/22] sve2.risu: Add patterns for multiply (indexed) ops,
Stephen Long <=
- [RISU PATCH v2 22/22] sve2.risu: Add patterns for scatter store insns, Stephen Long, 2020/05/21
- [RISU PATCH v2 16/22] sve2.risu: Add patterns for integer multiply-add (unpredicated) ops, Stephen Long, 2020/05/21
- [RISU PATCH v2 21/22] sve2.risu: Add patterns for gather load insns, Stephen Long, 2020/05/21
- [RISU PATCH v2 19/22] sve2.risu: Add patterns for integer compare ops, Stephen Long, 2020/05/21
- [RISU PATCH v2 20/22] sve2.risu: Add patterns for fp widening multiply-add ops, Stephen Long, 2020/05/21