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[PATCH RISU 1/4] sve2.risu: Add patterns for floating-point pairwise ops
From: |
Stephen Long |
Subject: |
[PATCH RISU 1/4] sve2.risu: Add patterns for floating-point pairwise ops |
Date: |
Tue, 19 May 2020 09:03:51 -0700 |
Signed-off-by: Stephen Long <address@hidden>
---
sve2.risu | 14 ++++++++++++++
1 file changed, 14 insertions(+)
create mode 100755 sve2.risu
diff --git a/sve2.risu b/sve2.risu
new file mode 100755
index 0000000..eb1d75a
--- /dev/null
+++ b/sve2.risu
@@ -0,0 +1,14 @@
+# Input file for risugen defining AArch64 SVE2 instructions
+.mode arm.aarch64
+
+# floating-point pairwise
+FADDP A64_V 01100100 size:2 010 000 100 pg:3 zm:5 zdn:5 \
+!constraints { $size != 0; }
+FMAXNMP A64_V 01100100 size:2 010 100 100 pg:3 zm:5 zdn:5 \
+!constraints { $size != 0; }
+FMINNMP A64_V 01100100 size:2 010 101 100 pg:3 zm:5 zdn:5 \
+!constraints { $size != 0; }
+FMAXP A64_V 01100100 size:2 010 110 100 pg:3 zm:5 zdn:5 \
+!constraints { $size != 0; }
+FMINP A64_V 01100100 size:2 010 111 100 pg:3 zm:5 zdn:5 \
+!constraints { $size != 0; }
--
2.25.1