Re: [PATCH 10/10] target/arm: Convert Neon one-register-and-immediate insns to decodetree

[Richard Henderson]

On 5/15/20 7:20 AM, Peter Maydell wrote:
> diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
> index f27fe769f85..f4eeb84541f 100644
> --- a/target/arm/translate-neon.inc.c
> +++ b/target/arm/translate-neon.inc.c
> @@ -1821,3 +1821,154 @@ DO_FP_2SH(VCVT_SF, gen_helper_vfp_sltos)
>  DO_FP_2SH(VCVT_UF, gen_helper_vfp_ultos)
>  DO_FP_2SH(VCVT_FS, gen_helper_vfp_tosls_round_to_zero)
>  DO_FP_2SH(VCVT_FU, gen_helper_vfp_touls_round_to_zero)
> +
> +static uint32_t asimd_imm_const(uint32_t imm, int cmode, int op)

It would be better to match AdvSIMDExpandImm and return uint64_t.

> +    case 14:
> +        imm |= (imm << 8) | (imm << 16) | (imm << 24);
> +        if (op) {
> +            imm = ~imm;
> +        }

You could then handle case 14 op == 1 properly here,

> +static bool trans_VMVN_14_1r(DisasContext *s, arg_1reg_imm *a)

and you wouldn't have to special case this at all.

> +{
> +  # Logic operations, ie not VMOV or VMVN: (cmode & 1) && cmode < 12
> +  VORR_1r        1111 001 . 1 . 000 ... .... 0001 0 . 0 1 .... \
> +                 @1reg_imm cmode=1 op=0
> +  VORR_1r        1111 001 . 1 . 000 ... .... 0011 0 . 0 1 .... \
> +                 @1reg_imm cmode=3 op=0
> +  VORR_1r        1111 001 . 1 . 000 ... .... 0101 0 . 0 1 .... \
> +                 @1reg_imm cmode=5 op=0
> +  VORR_1r        1111 001 . 1 . 000 ... .... 0111 0 . 0 1 .... \
> +                 @1reg_imm cmode=7 op=0
> +  VORR_1r        1111 001 . 1 . 000 ... .... 1001 0 . 0 1 .... \
> +                 @1reg_imm cmode=9 op=0
> +  VORR_1r        1111 001 . 1 . 000 ... .... 1011 0 . 0 1 .... \
> +                 @1reg_imm cmode=11 op=0
> +
> +  VBIC_1r        1111 001 . 1 . 000 ... .... 0001 0 . 1 1 .... \
> +                 @1reg_imm cmode=1 op=1
> +  VBIC_1r        1111 001 . 1 . 000 ... .... 0011 0 . 1 1 .... \
> +                 @1reg_imm cmode=3 op=1
> +  VBIC_1r        1111 001 . 1 . 000 ... .... 0101 0 . 1 1 .... \
> +                 @1reg_imm cmode=5 op=1
> +  VBIC_1r        1111 001 . 1 . 000 ... .... 0111 0 . 1 1 .... \
> +                 @1reg_imm cmode=7 op=1
> +  VBIC_1r        1111 001 . 1 . 000 ... .... 1001 0 . 1 1 .... \
> +                 @1reg_imm cmode=9 op=1
> +  VBIC_1r        1111 001 . 1 . 000 ... .... 1011 0 . 1 1 .... \
> +                 @1reg_imm cmode=11 op=1
> +
> +  # A VMVN special case: cmode == 14 op == 1
> +  VMVN_14_1r     1111 001 . 1 . 000 ... .... 1110 0 . 1 1 .... \
> +                 @1reg_imm cmode=14 op=1
> +
> +  # VMOV, VMVN: all other cmode/op combinations
> +  VMOV_1r        1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... \
> +                 @1reg_imm
> +}

I wonder if it's worth repeating VORR/VBIC so many times.
You can just as well do the (cmode & 1) && cmode < 12 check in the trans_ 
function.


r~