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[PATCH 07/10] target/arm: Convert Neon narrowing shifts with op==9 to de
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From: |
Peter Maydell |
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Subject: |
[PATCH 07/10] target/arm: Convert Neon narrowing shifts with op==9 to decodetree |
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Date: |
Fri, 15 May 2020 15:20:53 +0100 |
Convert the remaining Neon narrowing shifts to decodetree:
* VQSHRN
* VQRSHRN
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/neon-dp.decode | 32 ++++++++++
target/arm/translate-neon.inc.c | 15 +++++
target/arm/translate.c | 110 +-------------------------------
3 files changed, 49 insertions(+), 108 deletions(-)
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index f8d19c5819c..bf4ef8c555f 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -372,3 +372,35 @@ VQRSHRUN_32_2sh 1111 001 1 1 . 01 .... .... 1000 0 .
. 1 .... \
@2reg_shift_q1 size=2 shift=%neon_rshift_i4
VQRSHRUN_16_2sh 1111 001 1 1 . 001 ... .... 1000 0 . . 1 .... \
@2reg_shift_q1 size=1 shift=%neon_rshift_i3
+
+# VQSHRN with signed input
+VQSHRN_S64_2sh 1111 001 0 1 . 1 ..... .... 1001 0 . . 1 .... \
+ @2reg_shift_q0 size=3 shift=%neon_rshift_i5
+VQSHRN_S32_2sh 1111 001 0 1 . 01 .... .... 1001 0 . . 1 .... \
+ @2reg_shift_q0 size=2 shift=%neon_rshift_i4
+VQSHRN_S16_2sh 1111 001 0 1 . 001 ... .... 1001 0 . . 1 .... \
+ @2reg_shift_q0 size=1 shift=%neon_rshift_i3
+
+# VQRSHRN with signed input
+VQRSHRN_S64_2sh 1111 001 0 1 . 1 ..... .... 1001 0 . . 1 .... \
+ @2reg_shift_q1 size=3 shift=%neon_rshift_i5
+VQRSHRN_S32_2sh 1111 001 0 1 . 01 .... .... 1001 0 . . 1 .... \
+ @2reg_shift_q1 size=2 shift=%neon_rshift_i4
+VQRSHRN_S16_2sh 1111 001 0 1 . 001 ... .... 1001 0 . . 1 .... \
+ @2reg_shift_q1 size=1 shift=%neon_rshift_i3
+
+# VQSHRN with unsigned input
+VQSHRN_U64_2sh 1111 001 1 1 . 1 ..... .... 1001 0 . . 1 .... \
+ @2reg_shift_q0 size=3 shift=%neon_rshift_i5
+VQSHRN_U32_2sh 1111 001 1 1 . 01 .... .... 1001 0 . . 1 .... \
+ @2reg_shift_q0 size=2 shift=%neon_rshift_i4
+VQSHRN_U16_2sh 1111 001 1 1 . 001 ... .... 1001 0 . . 1 .... \
+ @2reg_shift_q0 size=1 shift=%neon_rshift_i3
+
+# VQRSHRN with unsigned input
+VQRSHRN_U64_2sh 1111 001 1 1 . 1 ..... .... 1001 0 . . 1 .... \
+ @2reg_shift_q1 size=3 shift=%neon_rshift_i5
+VQRSHRN_U32_2sh 1111 001 1 1 . 01 .... .... 1001 0 . . 1 .... \
+ @2reg_shift_q1 size=2 shift=%neon_rshift_i4
+VQRSHRN_U16_2sh 1111 001 1 1 . 001 ... .... 1001 0 . . 1 .... \
+ @2reg_shift_q1 size=1 shift=%neon_rshift_i3
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index 18ea7255e38..9a75a69a4f5 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -1672,3 +1672,18 @@ DO_2SN_32(VQSHRUN_16, gen_helper_neon_shl_s16,
gen_helper_neon_unarrow_sat8)
DO_2SN_64(VQRSHRUN_64, gen_helper_neon_rshl_s64, gen_helper_neon_unarrow_sat32)
DO_2SN_32(VQRSHRUN_32, gen_helper_neon_rshl_s32, gen_helper_neon_unarrow_sat16)
DO_2SN_32(VQRSHRUN_16, gen_helper_neon_rshl_s16, gen_helper_neon_unarrow_sat8)
+DO_2SN_64(VQSHRN_S64, gen_sshl_i64, gen_helper_neon_narrow_sat_s32)
+DO_2SN_32(VQSHRN_S32, gen_sshl_i32, gen_helper_neon_narrow_sat_s16)
+DO_2SN_32(VQSHRN_S16, gen_helper_neon_shl_s16, gen_helper_neon_narrow_sat_s8)
+
+DO_2SN_64(VQRSHRN_S64, gen_helper_neon_rshl_s64,
gen_helper_neon_narrow_sat_s32)
+DO_2SN_32(VQRSHRN_S32, gen_helper_neon_rshl_s32,
gen_helper_neon_narrow_sat_s16)
+DO_2SN_32(VQRSHRN_S16, gen_helper_neon_rshl_s16, gen_helper_neon_narrow_sat_s8)
+
+DO_2SN_64(VQSHRN_U64, gen_ushl_i64, gen_helper_neon_narrow_sat_u32)
+DO_2SN_32(VQSHRN_U32, gen_ushl_i32, gen_helper_neon_narrow_sat_u16)
+DO_2SN_32(VQSHRN_U16, gen_helper_neon_shl_u16, gen_helper_neon_narrow_sat_u8)
+
+DO_2SN_64(VQRSHRN_U64, gen_helper_neon_rshl_u64,
gen_helper_neon_narrow_sat_u32)
+DO_2SN_32(VQRSHRN_U32, gen_helper_neon_rshl_u32,
gen_helper_neon_narrow_sat_u16)
+DO_2SN_32(VQRSHRN_U16, gen_helper_neon_rshl_u16, gen_helper_neon_narrow_sat_u8)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index f884db535b4..f728231b198 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -3201,40 +3201,6 @@ static inline void gen_neon_unarrow_sats(int size,
TCGv_i32 dest, TCGv_i64 src)
}
}
-static inline void gen_neon_shift_narrow(int size, TCGv_i32 var, TCGv_i32
shift,
- int q, int u)
-{
- if (q) {
- if (u) {
- switch (size) {
- case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
- case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
- default: abort();
- }
- } else {
- switch (size) {
- case 1: gen_helper_neon_rshl_s16(var, var, shift); break;
- case 2: gen_helper_neon_rshl_s32(var, var, shift); break;
- default: abort();
- }
- }
- } else {
- if (u) {
- switch (size) {
- case 1: gen_helper_neon_shl_u16(var, var, shift); break;
- case 2: gen_ushl_i32(var, var, shift); break;
- default: abort();
- }
- } else {
- switch (size) {
- case 1: gen_helper_neon_shl_s16(var, var, shift); break;
- case 2: gen_sshl_i32(var, var, shift); break;
- default: abort();
- }
- }
- }
-}
-
static inline void gen_neon_widen(TCGv_i64 dest, TCGv_i32 src, int size, int u)
{
if (u) {
@@ -5281,6 +5247,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t
insn)
case 6: /* VQSHLU */
case 7: /* VQSHL */
case 8: /* VSHRN, VRSHRN, VQSHRUN, VQRSHRUN */
+ case 9: /* VQSHRN, VQRSHRN */
return 1; /* handled by decodetree */
default:
break;
@@ -5298,80 +5265,7 @@ static int disas_neon_data_insn(DisasContext *s,
uint32_t insn)
size--;
}
shift = (insn >> 16) & ((1 << (3 + size)) - 1);
- if (op < 10) {
- /* Shift by immediate and narrow:
- VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
- int input_unsigned = (op == 8) ? !u : u;
- if (rm & 1) {
- return 1;
- }
- shift = shift - (1 << (size + 3));
- size++;
- if (size == 3) {
- tmp64 = tcg_const_i64(shift);
- neon_load_reg64(cpu_V0, rm);
- neon_load_reg64(cpu_V1, rm + 1);
- for (pass = 0; pass < 2; pass++) {
- TCGv_i64 in;
- if (pass == 0) {
- in = cpu_V0;
- } else {
- in = cpu_V1;
- }
- if (q) {
- if (input_unsigned) {
- gen_helper_neon_rshl_u64(cpu_V0, in, tmp64);
- } else {
- gen_helper_neon_rshl_s64(cpu_V0, in, tmp64);
- }
- } else {
- if (input_unsigned) {
- gen_ushl_i64(cpu_V0, in, tmp64);
- } else {
- gen_sshl_i64(cpu_V0, in, tmp64);
- }
- }
- tmp = tcg_temp_new_i32();
- gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
- neon_store_reg(rd, pass, tmp);
- } /* for pass */
- tcg_temp_free_i64(tmp64);
- } else {
- if (size == 1) {
- imm = (uint16_t)shift;
- imm |= imm << 16;
- } else {
- /* size == 2 */
- imm = (uint32_t)shift;
- }
- tmp2 = tcg_const_i32(imm);
- tmp4 = neon_load_reg(rm + 1, 0);
- tmp5 = neon_load_reg(rm + 1, 1);
- for (pass = 0; pass < 2; pass++) {
- if (pass == 0) {
- tmp = neon_load_reg(rm, 0);
- } else {
- tmp = tmp4;
- }
- gen_neon_shift_narrow(size, tmp, tmp2, q,
- input_unsigned);
- if (pass == 0) {
- tmp3 = neon_load_reg(rm, 1);
- } else {
- tmp3 = tmp5;
- }
- gen_neon_shift_narrow(size, tmp3, tmp2, q,
- input_unsigned);
- tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3);
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(tmp3);
- tmp = tcg_temp_new_i32();
- gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
- neon_store_reg(rd, pass, tmp);
- } /* for pass */
- tcg_temp_free_i32(tmp2);
- }
- } else if (op == 10) {
+ if (op == 10) {
/* VSHLL, VMOVL */
if (q || (rd & 1)) {
return 1;
--
2.20.1
- Re: [PATCH 03/10] target/arm: Convert Neon VSHR 2-reg-shift insns to decodetree, (continued)
- [PATCH 04/10] target/arm: Convert Neon VSRA, VSRI, VRSHR, VRSRA 2-reg-shift insns to decodetree, Peter Maydell, 2020/05/15
- [PATCH 05/10] target/arm: Convert VQSHLU, VQSHL 2-reg-shift insns to decodetree, Peter Maydell, 2020/05/15
- [PATCH 06/10] target/arm: Convert Neon narrowing shifts with op==8 to decodetree, Peter Maydell, 2020/05/15
- [PATCH 08/10] target/arm: Convert Neon VSHLL, VMOVL to decodetree, Peter Maydell, 2020/05/15
- [PATCH 07/10] target/arm: Convert Neon narrowing shifts with op==9 to decodetree,
Peter Maydell <=
- [PATCH 09/10] target/arm: Convert VCVT fixed-point ops to decodetree, Peter Maydell, 2020/05/15
- [PATCH 10/10] target/arm: Convert Neon one-register-and-immediate insns to decodetree, Peter Maydell, 2020/05/15
- Re: [PATCH 00/10] target/arm: Convert 2-reg-shift and 1-reg-imm Neon insns to decodetree, no-reply, 2020/05/15