[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 05/45] target/arm: Remove unnecessary range check for VSHL
From: |
Peter Maydell |
Subject: |
[PULL 05/45] target/arm: Remove unnecessary range check for VSHL |
Date: |
Thu, 14 May 2020 15:20:58 +0100 |
From: Richard Henderson <address@hidden>
In 1dc8425e551, while converting to gvec, I added an extra range check
against the shift count. This was unnecessary because the encoding of
the shift count produces 0 to the element size - 1.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate.c | 12 ++----------
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 3c489852dce..2eec689c5ed 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -5752,16 +5752,8 @@ static int disas_neon_data_insn(DisasContext *s,
uint32_t insn)
gen_gvec_sli(size, rd_ofs, rm_ofs, shift,
vec_size, vec_size);
} else { /* VSHL */
- /* Shifts larger than the element size are
- * architecturally valid and results in zero.
- */
- if (shift >= 8 << size) {
- tcg_gen_gvec_dup_imm(size, rd_ofs,
- vec_size, vec_size, 0);
- } else {
- tcg_gen_gvec_shli(size, rd_ofs, rm_ofs, shift,
- vec_size, vec_size);
- }
+ tcg_gen_gvec_shli(size, rd_ofs, rm_ofs, shift,
+ vec_size, vec_size);
}
return 0;
}
--
2.20.1
- [PULL 00/45] target-arm queue, Peter Maydell, 2020/05/14
- [PULL 01/45] target/arm: Use correct GDB XML for M-profile cores, Peter Maydell, 2020/05/14
- [PULL 02/45] target/arm: Create gen_gvec_[us]sra, Peter Maydell, 2020/05/14
- [PULL 03/45] target/arm: Create gen_gvec_{u,s}{rshr,rsra}, Peter Maydell, 2020/05/14
- [PULL 04/45] target/arm: Create gen_gvec_{sri,sli}, Peter Maydell, 2020/05/14
- [PULL 05/45] target/arm: Remove unnecessary range check for VSHL,
Peter Maydell <=
- [PULL 06/45] target/arm: Tidy handle_vec_simd_shri, Peter Maydell, 2020/05/14
- [PULL 07/45] target/arm: Create gen_gvec_{ceq,clt,cle,cgt,cge}0, Peter Maydell, 2020/05/14
- [PULL 08/45] target/arm: Create gen_gvec_{mla,mls}, Peter Maydell, 2020/05/14
- [PULL 09/45] target/arm: Swap argument order for VSHL during decode, Peter Maydell, 2020/05/14
- [PULL 10/45] target/arm: Create gen_gvec_{cmtst,ushl,sshl}, Peter Maydell, 2020/05/14
- [PULL 11/45] target/arm: Create gen_gvec_{uqadd, sqadd, uqsub, sqsub}, Peter Maydell, 2020/05/14
- [PULL 12/45] target/arm: Remove fp_status from helper_{recpe, rsqrte}_u32, Peter Maydell, 2020/05/14
- [PULL 13/45] target/arm: Create gen_gvec_{qrdmla,qrdmls}, Peter Maydell, 2020/05/14
- [PULL 15/45] target/arm: Clear tail in gvec_fmul_idx_*, gvec_fmla_idx_*, Peter Maydell, 2020/05/14
- [PULL 14/45] target/arm: Pass pointer to qc to qrdmla/qrdmls, Peter Maydell, 2020/05/14