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[PULL 06/34] hw/timer/nrf51_timer: Display timer ID in trace events
From: |
Peter Maydell |
Subject: |
[PULL 06/34] hw/timer/nrf51_timer: Display timer ID in trace events |
Date: |
Mon, 11 May 2020 14:33:37 +0100 |
From: Philippe Mathieu-Daudé <address@hidden>
The NRF51 series SoC have 3 timer peripherals, each having
4 counters. To help differentiate which peripheral is accessed,
display the timer ID in the trace events.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
include/hw/timer/nrf51_timer.h | 1 +
hw/arm/nrf51_soc.c | 5 +++++
hw/timer/nrf51_timer.c | 11 +++++++++--
hw/timer/trace-events | 4 ++--
4 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/include/hw/timer/nrf51_timer.h b/include/hw/timer/nrf51_timer.h
index 85cad2300df..eb6815f21d7 100644
--- a/include/hw/timer/nrf51_timer.h
+++ b/include/hw/timer/nrf51_timer.h
@@ -59,6 +59,7 @@ typedef struct NRF51TimerState {
MemoryRegion iomem;
qemu_irq irq;
+ uint8_t id;
QEMUTimer timer;
int64_t timer_start_ns;
int64_t update_counter_ns;
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
index e50473fd199..71309e53cc8 100644
--- a/hw/arm/nrf51_soc.c
+++ b/hw/arm/nrf51_soc.c
@@ -150,6 +150,11 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error
**errp)
/* TIMER */
for (i = 0; i < NRF51_NUM_TIMERS; i++) {
+ object_property_set_uint(OBJECT(&s->timer[i]), i, "id", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
if (err) {
error_propagate(errp, err);
diff --git a/hw/timer/nrf51_timer.c b/hw/timer/nrf51_timer.c
index bc82c85a6f2..38cea0542e1 100644
--- a/hw/timer/nrf51_timer.c
+++ b/hw/timer/nrf51_timer.c
@@ -17,6 +17,7 @@
#include "hw/arm/nrf51.h"
#include "hw/irq.h"
#include "hw/timer/nrf51_timer.h"
+#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "trace.h"
@@ -185,7 +186,7 @@ static uint64_t nrf51_timer_read(void *opaque, hwaddr
offset, unsigned int size)
__func__, offset);
}
- trace_nrf51_timer_read(offset, r, size);
+ trace_nrf51_timer_read(s->id, offset, r, size);
return r;
}
@@ -197,7 +198,7 @@ static void nrf51_timer_write(void *opaque, hwaddr offset,
uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
size_t idx;
- trace_nrf51_timer_write(offset, value, size);
+ trace_nrf51_timer_write(s->id, offset, value, size);
switch (offset) {
case NRF51_TIMER_TASK_START:
@@ -372,12 +373,18 @@ static const VMStateDescription vmstate_nrf51_timer = {
}
};
+static Property nrf51_timer_properties[] = {
+ DEFINE_PROP_UINT8("id", NRF51TimerState, id, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void nrf51_timer_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = nrf51_timer_reset;
dc->vmsd = &vmstate_nrf51_timer;
+ device_class_set_props(dc, nrf51_timer_properties);
}
static const TypeInfo nrf51_timer_info = {
diff --git a/hw/timer/trace-events b/hw/timer/trace-events
index 29fda7870e0..43b605cc759 100644
--- a/hw/timer/trace-events
+++ b/hw/timer/trace-events
@@ -67,8 +67,8 @@ cmsdk_apb_dualtimer_write(uint64_t offset, uint64_t data,
unsigned size) "CMSDK
cmsdk_apb_dualtimer_reset(void) "CMSDK APB dualtimer: reset"
# nrf51_timer.c
-nrf51_timer_read(uint64_t addr, uint32_t value, unsigned size) "read addr 0x%"
PRIx64 " data 0x%" PRIx32 " size %u"
-nrf51_timer_write(uint64_t addr, uint32_t value, unsigned size) "write addr
0x%" PRIx64 " data 0x%" PRIx32 " size %u"
+nrf51_timer_read(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned
size) "timer %u read addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
+nrf51_timer_write(uint8_t timer_id, uint64_t addr, uint32_t value, unsigned
size) "timer %u write addr 0x%" PRIx64 " data 0x%" PRIx32 " size %u"
# bcm2835_systmr.c
bcm2835_systmr_irq(bool enable) "timer irq state %u"
--
2.20.1
- [PULL 00/34] target-arm queue, Peter Maydell, 2020/05/11
- [PULL 01/34] aspeed: Add boot stub for smp booting, Peter Maydell, 2020/05/11
- [PULL 02/34] target/arm: Drop access_el3_aa32ns_aa64any(), Peter Maydell, 2020/05/11
- [PULL 04/34] aspeed: sdmc: Implement AST2600 locking behaviour, Peter Maydell, 2020/05/11
- [PULL 03/34] aspeed: Support AST2600A1 silicon revision, Peter Maydell, 2020/05/11
- [PULL 05/34] hw/arm/nrf51: Add NRF51_PERIPHERAL_SIZE definition, Peter Maydell, 2020/05/11
- [PULL 06/34] hw/timer/nrf51_timer: Display timer ID in trace events,
Peter Maydell <=
- [PULL 08/34] exec: Add block comments for watchpoint routines, Peter Maydell, 2020/05/11
- [PULL 09/34] exec: Fix cpu_watchpoint_address_matches address length, Peter Maydell, 2020/05/11
- [PULL 10/34] accel/tcg: Add block comment for probe_access, Peter Maydell, 2020/05/11
- [PULL 11/34] accel/tcg: Adjust probe_access call to page_check_range, Peter Maydell, 2020/05/11
- [PULL 07/34] hw/timer/nrf51_timer: Add trace event of counter value update, Peter Maydell, 2020/05/11
- [PULL 13/34] accel/tcg: Add endian-specific cpu_{ld, st}* operations, Peter Maydell, 2020/05/11
- [PULL 15/34] target/arm: Drop manual handling of set/clear_helper_retaddr, Peter Maydell, 2020/05/11
- [PULL 14/34] target/arm: Use cpu_*_data_ra for sve_ldst_tlb_fn, Peter Maydell, 2020/05/11
- [PULL 16/34] target/arm: Add sve infrastructure for page lookup, Peter Maydell, 2020/05/11
- [PULL 18/34] target/arm: Use SVEContLdSt in sve_ld1_r, Peter Maydell, 2020/05/11