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[PATCH v2 2/4] target/arm: Use tcg_gen_gvec_mov for clear_vec_high
From: |
Richard Henderson |
Subject: |
[PATCH v2 2/4] target/arm: Use tcg_gen_gvec_mov for clear_vec_high |
Date: |
Thu, 7 May 2020 10:23:50 -0700 |
The 8-byte store for the end a !is_q operation can be
merged with the other stores. Use a no-op vector move
to trigger the expand_clr portion of tcg_gen_gvec_mov.
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-a64.c | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 62e5729904..b6feb2b9dc 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -496,14 +496,8 @@ static void clear_vec_high(DisasContext *s, bool is_q, int
rd)
unsigned ofs = fp_reg_offset(s, rd, MO_64);
unsigned vsz = vec_full_reg_size(s);
- if (!is_q) {
- TCGv_i64 tcg_zero = tcg_const_i64(0);
- tcg_gen_st_i64(tcg_zero, cpu_env, ofs + 8);
- tcg_temp_free_i64(tcg_zero);
- }
- if (vsz > 16) {
- tcg_gen_gvec_dup_imm(MO_64, ofs + 16, vsz - 16, vsz - 16, 0);
- }
+ /* Nop move, with side effect of clearing the tail. */
+ tcg_gen_gvec_mov(MO_64, ofs, ofs, is_q ? 16 : 8, vsz);
}
void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v)
--
2.20.1
- [PATCH v2 0/4] target/arm: Misc cleanups, Richard Henderson, 2020/05/07
- [PATCH v2 2/4] target/arm: Use tcg_gen_gvec_mov for clear_vec_high,
Richard Henderson <=
- [PATCH v2 1/4] target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA, Richard Henderson, 2020/05/07
- [PATCH v2 3/4] target/arm: Use clear_vec_high more effectively, Richard Henderson, 2020/05/07
- [PATCH v2 4/4] target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed), Richard Henderson, 2020/05/07
- Re: [PATCH v2 0/4] target/arm: Misc cleanups, Richard Henderson, 2020/05/07
- Re: [PATCH v2 0/4] target/arm: Misc cleanups, Peter Maydell, 2020/05/11