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[PATCH 04/36] target/arm: Convert VCMLA (vector) to decodetree
From: |
Peter Maydell |
Subject: |
[PATCH 04/36] target/arm: Convert VCMLA (vector) to decodetree |
Date: |
Thu, 30 Apr 2020 19:09:31 +0100 |
Convert the VCMLA (vector) insns in the 3same extension group to
decodetree.
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-neon.inc.c | 37 +++++++++++++++++++++++++++++++++
target/arm/translate.c | 11 +---------
target/arm/neon-shared.decode | 11 ++++++++++
3 files changed, 49 insertions(+), 10 deletions(-)
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index a33e81ba3ab..0baae1338a3 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -30,3 +30,40 @@
#include "decode-neon-dp.inc.c"
#include "decode-neon-ls.inc.c"
#include "decode-neon-shared.inc.c"
+
+static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a)
+{
+ int opr_sz;
+ TCGv_ptr fpst;
+ gen_helper_gvec_3_ptr *fn_gvec_ptr;
+
+ if (!dc_isar_feature(aa32_vcma, s)
+ || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vn | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if ((a->vn | a->vm | a->vd) & a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ opr_sz = (1 + a->q) * 8;
+ fpst = get_fpstatus_ptr(1);
+ fn_gvec_ptr = a->size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah;
+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
+ vfp_reg_offset(1, a->vn),
+ vfp_reg_offset(1, a->vm),
+ fpst, opr_sz, opr_sz, a->rot,
+ fn_gvec_ptr);
+ tcg_temp_free_ptr(fpst);
+ return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index bd766391e9e..17167634e29 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7048,16 +7048,7 @@ static int disas_neon_insn_3same_ext(DisasContext *s,
uint32_t insn)
bool is_long = false, q = extract32(insn, 6, 1);
bool ptr_is_env = false;
- if ((insn & 0xfe200f10) == 0xfc200800) {
- /* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */
- int size = extract32(insn, 20, 1);
- data = extract32(insn, 23, 2); /* rot */
- if (!dc_isar_feature(aa32_vcma, s)
- || (!size && !dc_isar_feature(aa32_fp16_arith, s))) {
- return 1;
- }
- fn_gvec_ptr = size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah;
- } else if ((insn & 0xfea00f10) == 0xfc800800) {
+ if ((insn & 0xfea00f10) == 0xfc800800) {
/* VCADD -- 1111 110R 1.0S .... .... 1000 ...0 .... */
int size = extract32(insn, 20, 1);
data = extract32(insn, 24, 1); /* rot */
diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
index 3aea7c5e188..d1d707a56d5 100644
--- a/target/arm/neon-shared.decode
+++ b/target/arm/neon-shared.decode
@@ -25,3 +25,14 @@
# More specifically, this covers:
# 2reg scalar ext: 0b1111_1110_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx
# 3same ext: 0b1111_110x_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx
+
+# VFP/Neon register fields; same as vfp.decode
+%vm_dp 5:1 0:4
+%vm_sp 0:4 5:1
+%vn_dp 7:1 16:4
+%vn_sp 16:4 7:1
+%vd_dp 22:1 12:4
+%vd_sp 12:4 22:1
+
+VCMLA 1111 110 rot:2 . 1 size:1 .... .... 1000 . q:1 . 0 .... \
+ vm=%vm_dp vn=%vn_dp vd=%vd_dp
--
2.20.1
- [PATCH 00/36] target/arm: Convert Neon to decodetree (part 1), Peter Maydell, 2020/04/30
- [PATCH 01/36] target/arm/translate-vfp.inc.c: Remove duplicate simd_r32 check, Peter Maydell, 2020/04/30
- [PATCH 04/36] target/arm: Convert VCMLA (vector) to decodetree,
Peter Maydell <=
- [PATCH 02/36] target/arm: Don't allow Thumb Neon insns without FEATURE_NEON, Peter Maydell, 2020/04/30
- [PATCH 05/36] target/arm: Convert VCADD (vector) to decodetree, Peter Maydell, 2020/04/30
- [PATCH 03/36] target/arm: Add stubs for AArch32 Neon decodetree, Peter Maydell, 2020/04/30
- [PATCH 06/36] target/arm: Convert V[US]DOT (vector) to decodetree, Peter Maydell, 2020/04/30
- [PATCH 09/36] target/arm: Convert V[US]DOT (scalar) to decodetree, Peter Maydell, 2020/04/30