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[PATCH for-5.1 V2 3/7] hw/mips: Add CPU IRQ3 delivery for KVM
From: |
Huacai Chen |
Subject: |
[PATCH for-5.1 V2 3/7] hw/mips: Add CPU IRQ3 delivery for KVM |
Date: |
Thu, 30 Apr 2020 18:22:31 +0800 |
Currently, KVM/MIPS only deliver I/O interrupt via IP2, this patch add
IP3 delivery as well, because Loongson-3 based machine use both IRQ2
(CPU's IP2) and IRQ3 (CPU's IP3).
Signed-off-by: Huacai Chen <address@hidden>
Co-developed-by: Jiaxun Yang <address@hidden>
---
hw/mips/mips_int.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c
index 796730b..5526219 100644
--- a/hw/mips/mips_int.c
+++ b/hw/mips/mips_int.c
@@ -48,16 +48,14 @@ static void cpu_mips_irq_request(void *opaque, int irq, int
level)
if (level) {
env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
- if (kvm_enabled() && irq == 2) {
+ if (kvm_enabled() && (irq == 2 || irq == 3))
kvm_mips_set_interrupt(cpu, irq, level);
- }
} else {
env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
- if (kvm_enabled() && irq == 2) {
+ if (kvm_enabled() && (irq == 2 || irq == 3))
kvm_mips_set_interrupt(cpu, irq, level);
- }
}
if (env->CP0_Cause & CP0Ca_IP_mask) {
--
2.7.0
- [PATCH for-5.1 V2 0/7] mips: Add Loongson-3 machine support (with KVM), Huacai Chen, 2020/04/30
- [PATCH for-5.1 V2 1/7] configure: Add KVM target support for MIPS64, Huacai Chen, 2020/04/30
- [PATCH for-5.1 V2 2/7] hw/mips: Implement the kvm_type() hook in MachineClass, Huacai Chen, 2020/04/30
- [PATCH for-5.1 V2 3/7] hw/mips: Add CPU IRQ3 delivery for KVM,
Huacai Chen <=
- [PATCH for-5.1 V2 4/7] target/mips: Add Loongson-3 CPU definition, Huacai Chen, 2020/04/30
- [PATCH for-5.1 V2 5/7] target/mips: Add more CP0 register for save/restore, Huacai Chen, 2020/04/30
- [PATCH for-5.1 V2 6/7] hw/mips: Add Loongson-3 machine support (with KVM), Huacai Chen, 2020/04/30
- [PATCH for-5.1 V2 7/7] MAINTAINERS: Add myself as Loongson-3 maintainer, Huacai Chen, 2020/04/30
- Re: [PATCH for-5.1 V2 0/7] mips: Add Loongson-3 machine support (with KVM), no-reply, 2020/04/30