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[PULL v1 6/6] target/microblaze: Add the pvr-user2 property
From: |
Edgar E. Iglesias |
Subject: |
[PULL v1 6/6] target/microblaze: Add the pvr-user2 property |
Date: |
Thu, 30 Apr 2020 12:19:49 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
Add the pvr-user2 property to control the user-defined
PVR1 User2 register.
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target/microblaze/cpu.h | 1 +
target/microblaze/cpu.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 7bb5a3d6c6..a31134b65c 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -308,6 +308,7 @@ struct MicroBlazeCPU {
bool div_zero_exception;
bool unaligned_exceptions;
uint8_t pvr_user1;
+ uint32_t pvr_user2;
char *version;
uint8_t pvr;
} cfg;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index df5ee21dd6..aa9983069a 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -196,6 +196,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
(cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) |
cpu->cfg.pvr_user1;
+ env->pvr.regs[1] = cpu->cfg.pvr_user2;
env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
(cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
(cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
@@ -294,6 +295,7 @@ static Property mb_properties[] = {
DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0),
+ DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0),
DEFINE_PROP_END_OF_LIST(),
};
--
2.20.1
- [PULL v1 0/6] Xilinx queue 2020-04-30, Edgar E. Iglesias, 2020/04/30
- [PULL v1 1/6] target/microblaze: Add the opcode-0x0-illegal CPU property, Edgar E. Iglesias, 2020/04/30
- [PULL v1 3/6] target/microblaze: Add the div-zero-exception property, Edgar E. Iglesias, 2020/04/30
- [PULL v1 2/6] target/microblaze: Add the ill-opcode-exception property, Edgar E. Iglesias, 2020/04/30
- [PULL v1 4/6] target/microblaze: Add the unaligned-exceptions property, Edgar E. Iglesias, 2020/04/30
- [PULL v1 6/6] target/microblaze: Add the pvr-user2 property,
Edgar E. Iglesias <=
- [PULL v1 5/6] target/microblaze: Add the pvr-user1 property, Edgar E. Iglesias, 2020/04/30
- Re: [PULL v1 0/6] Xilinx queue 2020-04-30, Peter Maydell, 2020/04/30