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[PULL v2 07/14] hw/riscv: Generate correct "mmu-type" for 32-bit machine
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From: |
Alistair Francis |
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Subject: |
[PULL v2 07/14] hw/riscv: Generate correct "mmu-type" for 32-bit machines |
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Date: |
Wed, 29 Apr 2020 13:19:59 -0700 |
From: Bin Meng <address@hidden>
32-bit machine should have its CPU's "mmu-type" set to "riscv,sv32".
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Message-Id: <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
---
hw/riscv/sifive_u.c | 4 ++++
hw/riscv/spike.c | 4 ++++
hw/riscv/virt.c | 4 ++++
3 files changed, 12 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 8d0ee8b9c4..e32355a691 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -160,7 +160,11 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
qemu_fdt_add_subnode(fdt, nodename);
/* cpu 0 is the management hart that does not have mmu */
if (cpu != 0) {
+#if defined(TARGET_RISCV32)
+ qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
+#else
qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
+#endif
isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
} else {
isa = riscv_isa_string(&s->soc.e_cpus.harts[0]);
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 5053fe4590..98697a244e 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -102,7 +102,11 @@ static void create_fdt(SpikeState *s, const struct
MemmapEntry *memmap,
char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
char *isa = riscv_isa_string(&s->soc.harts[cpu]);
qemu_fdt_add_subnode(fdt, nodename);
+#if defined(TARGET_RISCV32)
+ qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
+#else
qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
+#endif
qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 85ec9e22aa..c621a970aa 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -229,7 +229,11 @@ static void create_fdt(RISCVVirtState *s, const struct
MemmapEntry *memmap,
char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
char *isa = riscv_isa_string(&s->soc.harts[cpu]);
qemu_fdt_add_subnode(fdt, nodename);
+#if defined(TARGET_RISCV32)
+ qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
+#else
qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
+#endif
qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
--
2.26.2
- [PULL v2 00/14] RISC-V Patch Queue for 5.1, Alistair Francis, 2020/04/29
- [PULL v2 02/14] riscv/sifive_u: Add a serial property to the sifive_u SoC, Alistair Francis, 2020/04/29
- [PULL v2 01/14] riscv/sifive_u: Fix up file ordering, Alistair Francis, 2020/04/29
- [PULL v2 06/14] riscv: Fix Stage2 SV32 page table walk, Alistair Francis, 2020/04/29
- [PULL v2 05/14] riscv: AND stage-1 and stage-2 protection flags, Alistair Francis, 2020/04/29
- [PULL v2 10/14] linux-user/riscv: fix up struct target_ucontext definition, Alistair Francis, 2020/04/29
- [PULL v2 03/14] riscv/sifive_u: Add a serial property to the sifive_u machine, Alistair Francis, 2020/04/29
- [PULL v2 07/14] hw/riscv: Generate correct "mmu-type" for 32-bit machines,
Alistair Francis <=
- [PULL v2 09/14] target/riscv: Add a sifive-e34 cpu type, Alistair Francis, 2020/04/29
- [PULL v2 04/14] riscv: Don't use stage-2 PTE lookup protection flags, Alistair Francis, 2020/04/29
- [PULL v2 08/14] riscv: sifive_e: Support changing CPU type, Alistair Francis, 2020/04/29
- [PULL v2 12/14] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware(), Alistair Francis, 2020/04/29
- [PULL v2 13/14] hw/riscv/spike: Allow loading firmware separately using -bios option, Alistair Francis, 2020/04/29
- [PULL v2 14/14] hw/riscv/spike: Allow more than one CPUs, Alistair Francis, 2020/04/29
- [PULL v2 11/14] roms: opensbi: Upgrade from v0.6 to v0.7, Alistair Francis, 2020/04/29
- Re: [PULL v2 00/14] RISC-V Patch Queue for 5.1, Peter Maydell, 2020/04/30